Datasheet

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29-14. SCI Flags Register (SCIFLR) [offset = 1Ch]......................................................................... 1466
29-15. SCI Interrupt Vector Offset 0 (SCIINTVECT0) [offset = 20h]...................................................... 1470
29-16. SCI Interrupt Vector Offset 1 (SCIINTVECT1) [offset = 24h]...................................................... 1470
29-17. SCI Format Control Register (SCIFORMAT) [offset = 28h] ....................................................... 1471
29-18. Baud Rate Selection Register (BRS) [offset = 2Ch] ................................................................ 1472
29-19. Receiver Emulation Data Buffer (SCIED) [offset = 30h] ........................................................... 1473
29-20. Receiver Data Buffer (SCIRD) [offset = 34h] ........................................................................ 1473
29-21. Transmit Data Buffer Register (SCITD) [offset = 38h].............................................................. 1474
29-22. SCI Pin I/O Control Register 0 (SCIPIO0) [offset = 3Ch] ......................................................... 1474
29-23. SCI Pin I/O Control Register 1 (SCIPIO1) [offset = 40h]........................................................... 1475
29-24. SCI Pin I/O Control Register 2 (SCIPIO2) [offset = 44h] .......................................................... 1476
29-25. SCI Pin I/O Control Register 3 (SCIPIO3) [offset = 48h]........................................................... 1477
29-26. SCI Pin I/O Control Register 4 (SCIPIO4) [offset = 4Ch] ......................................................... 1478
29-27. SCI Pin I/O Control Register 5 (SCIPIO5) [offset = 50h]........................................................... 1479
29-28. SCI Pin I/O Control Register 6 (SCIPIO6) [offset = 54h] .......................................................... 1480
29-29. SCI Pin I/O Control Register 7 (SCIPIO7) [offset = 58h]........................................................... 1481
29-30. SCI Pin I/O Control Register 8 (SCIPIO8) [offset = 5Ch] ......................................................... 1481
29-31. Input/Output Error Enable Register (IODFTCTRL) [offset = 90h]................................................. 1482
29-32. GPIO Functionality ...................................................................................................... 1484
30-1. Multiple I2C Modules Connection Diagram .......................................................................... 1487
30-2. Simple I2C Block Diagram ............................................................................................. 1489
30-3. Clocking Diagram for the I2C Module ................................................................................ 1490
30-4. Bit Transfer on the I2C Bus............................................................................................ 1491
30-5. I2C Module START and STOP Conditions .......................................................................... 1492
30-6. I2C Module Data Transfer .............................................................................................. 1492
30-7. I2C Module 7-Bit Addressing Format................................................................................. 1493
30-8. I2C Module 10-bit Addressing Format................................................................................ 1493
30-9. I2C Module 7-Bit Addressing Format with Repeated START ..................................................... 1493
30-10. I2C Module in Free Data Format...................................................................................... 1494
30-11. Arbitration Procedure Between Two Master Transmitters ......................................................... 1497
30-12. Synchronization of Two I2C Clock Generators During Arbitration ................................................ 1498
30-13. I2C Own Address Manager Register (I2COAR) [offset = 00] ..................................................... 1503
30-14. I2C Interrupt Mask Register (I2CIMR) [offset = 04h] ............................................................... 1504
30-15. I2C Status Register (I2CSR) [offset = 08h] .......................................................................... 1505
30-16. I2C Clock Divider Low Register (I2CCKL) [offset = 0Ch] .......................................................... 1508
30-17. I2C Clock Control High Register (I2CCKH) [offset = 10h] ......................................................... 1508
30-18. I2C Data Count Register (I2CCNT) [offset = 14h] .................................................................. 1509
30-19. I2C Data Receive Register (I2CDRR) [offset = 18h] ............................................................... 1509
30-20. I2C Slave Address Register (I2CSAR) [offset = 1Ch] .............................................................. 1510
30-21. I2C Data Transmit Register (I2CDXR) [offset = 20h]............................................................... 1510
30-22. I2C Mode Register (I2CMDR) [offset = 24h]......................................................................... 1511
30-23. Typical Timing Diagram of Repeat Mode ............................................................................ 1513
30-24. I2C Interrupt Vector Register (I2CIVR) [offset = 28h] .............................................................. 1514
30-25. I2C Extended Mode Register (I2CEMDR) [offset = 2Ch] .......................................................... 1515
30-26. I2C Prescale Register (I2CPSC) [offset = 30h] ..................................................................... 1515
30-27. I2C Peripheral ID Register 1 (I2CPID1) [offset = 34h] ............................................................. 1516
30-28. I2C Peripheral ID Register 2 (I2CPID2) [offset = 38h] ............................................................. 1516
30-29. I2C DMA Control Register (I2CDMACR) [offset = 3Ch]............................................................ 1517
30-30. I2C Pin Function Register (I2CPFNC) [offset = 48h] ............................................................... 1517
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List of Figures SPNU562–May 2014
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