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28-25. LIN Message Frame Showing LIN Interrupt Timing and Sequence .............................................. 1380
28-26. Wakeup Signal Generation ............................................................................................ 1384
28-27. GPIO Functionality ...................................................................................................... 1386
28-28. SCI Global Control Register 0 (SCIGCR0) (offset = 00) ........................................................... 1389
28-29. SCI Global Control Register 1 (SCIGCR1) (offset = 04h) ......................................................... 1390
28-30. SCI Global Control Register 2 (SCIGCR2) (offset = 08h) ......................................................... 1394
28-31. SCI Set Interrupt Register (SCISETINT) (offset = 0Ch)............................................................ 1396
28-32. SCI Clear Interrupt Register (SCICLEARINT) (offset = 10h) ...................................................... 1399
28-33. SCI Set Interrupt Level Register (SCISETINTLVL) (offset = 14h) ................................................ 1402
28-34. SCI Clear Interrupt Level Register (SCICLEARINTLVL) (offset = 18h) .......................................... 1405
28-35. SCI Flags Register (SCIFLR) (offset = 1Ch) ........................................................................ 1408
28-36. SCI Interrupt Vector Offset 0 (SCIINTVECT0) (offset = 20h) ..................................................... 1415
28-37. SCI Interrupt Vector Offset 1 (SCIINTVECT1) (offset = 24h) ..................................................... 1415
28-38. SCI Format Control Register (SCIFORMAT) (offset = 28h) ....................................................... 1416
28-39. Baud Rate Selection Register (BRS) (offset = 2Ch)................................................................ 1417
28-40. Receiver Emulation Data Buffer (SCIED) (offset = 30h) ........................................................... 1419
28-41. Receiver Data Buffer (SCIRD) (offset = 34h)........................................................................ 1419
28-42. Transmit Data Buffer Register (SCITD) (offset = 38h) ............................................................. 1420
28-43. SCI Pin I/O Control Register 0 (SCIPIO0) (offset = 3Ch).......................................................... 1420
28-44. SCI Pin I/O Control Register 1 (SCIPIO1) (offset = 40h) .......................................................... 1421
28-45. SCI Pin I/O Control Register 2 (SCIPIO2) (offset = 44h) .......................................................... 1422
28-46. SCI Pin I/O Control Register 3 (SCIPIO3) (offset = 48h) .......................................................... 1423
28-47. SCI Pin I/O Control Register 4 (SCIPIO4) (offset = 4Ch).......................................................... 1424
28-48. SCI Pin I/O Control Register 5 (SCIPIO5) (offset = 50h) .......................................................... 1425
28-49. SCI Pin I/O Control Register 6 (SCIPIO6) (offset = 54h) .......................................................... 1426
28-50. SCI Pin I/O Control Register 7 (SCIPIO7) (offset = 58h) .......................................................... 1427
28-51. SCI Pin I/O Control Register 8 (SCIPIO8) (offset = 5Ch).......................................................... 1428
28-52. LIN Compare Register (LINCOMPARE) (offset = 60h) ............................................................ 1429
28-53. LIN Receive Buffer 0 Register (LINRD0) (offset = 64h)............................................................ 1430
28-54. LIN Receive Buffer 1 Register (RD1) (offset = 68h) ................................................................ 1431
28-55. LIN Mask Register (LINMASK) (offset = 6Ch)....................................................................... 1432
28-56. LIN Identification Register (LINID) (offset = 70h) ................................................................... 1433
28-57. LIN Transmit Buffer 0 Register (LINTD0) (offset = 74h) ........................................................... 1434
28-58. LIN Transmit Buffer 1 Register (LINTD1) (offset = 78h) ........................................................... 1434
28-59. Maximum Baud Rate Selection Register (MBRS) (offset = 7Ch) ................................................. 1435
28-60. Input/Output Error Enable Register (IODFTCTRL) (offset = 90h) ................................................ 1436
29-1. Detailed SCI Block Diagram ........................................................................................... 1440
29-2. Typical SCI Data Frame Formats ..................................................................................... 1441
29-3. Asynchronous Communication Bit Timing ........................................................................... 1442
29-4. Idle-Line Multiprocessor Communication Format ................................................................... 1444
29-5. Address-Bit Multiprocessor Communication Format................................................................ 1445
29-6. General Interrupt Scheme.............................................................................................. 1446
29-7. Interrupt Generation for Given Flags ................................................................................. 1447
29-8. SCI Global Control Register 0 (SCIGCR0) [offset = 00] ........................................................... 1455
29-9. SCI Global Control Register 1 (SCIGCR1) [offset = 04h].......................................................... 1456
29-10. SCI Set Interrupt Register (SCISETINT) [offset = 0Ch] ............................................................ 1459
29-11. SCI Clear Interrupt Register (SCICLEARINT) [offset = 10h] ...................................................... 1461
29-12. SCI Set Interrupt Level Register (SCISETINTLVL) [offset = 14h] ................................................ 1463
29-13. SCI Clear Interrupt Level Register (SCICLEARINTLVL) [offset = 18h] .......................................... 1464
57
SPNU562–May 2014 List of Figures
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