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27-79. SPI Extended Prescale Register 1 (EXTENDED_PRESCALE1 for SPIFMT0 and SPIFMT1) [offset =
138h] ...................................................................................................................... 1320
27-80. SPI Extended Prescale Register 2 (EXTENDED_PRESCALE2 for SPIFMT2 and SPIFMT3) [offset =
13Ch]...................................................................................................................... 1322
27-81. ECC Diagnostic Control Register (ECCDIAG_CTRL) [offset = 140h]............................................ 1323
27-82. ECC Diagnostic Status Register (ECCDIAG_STAT) [offset = 144h] ............................................. 1324
27-83. Single Bit Error Address Register - RXRAM (SBERRADDR1) [offset = 148h].................................. 1325
27-84. Single Bit Error Address Register - TXRAM (SBERRADDR0) [offset = 14Ch] ................................. 1326
27-85. Multi-buffer RAM Configuration When Parity Check is Supported................................................ 1327
27-86. Multi-buffer RAM Configuration When ECC Check is Supported................................................. 1327
27-87. Multi-buffer RAM Transmit Data Register [offset = Base + 000-1FFh]........................................... 1329
27-88. Multi-buffer RAM Receive Buffer Register [offset = RAM Base + 200-3FFh] ................................... 1331
27-89. Memory-Map for Parity Locations During Normal and Test Mode While EXTENDED_BUF Mode is
Disabled or the Feature is Not Implemented ........................................................................ 1334
27-90. Memory-Map for Parity Locations During Normal and Test Mode While EXTENDED_BUF Mode is
Enabled................................................................................................................... 1335
27-91. Example of Memory-Mapped Parity Locations During Test Mode................................................ 1336
27-92. Example of ECC Bit Locations During Test Mode .................................................................. 1337
27-93. SPI/MibSPI Pins During Master Mode 3-Pin Configuration........................................................ 1338
27-94. SPI/MibSPI Pins During Master Mode 4-Pin with SPISCS Configuation ........................................ 1338
27-95. SPI/MibSPI Pins During Master Mode in 4-Pin with SPIENA Configuration .................................... 1339
27-96. SPI/MibSPI Pins During Master/Slave Mode with 5-Pin Configuration .......................................... 1339
27-97. SPI/MibSPI Pins During Slave Mode 3-Pin Configuration ......................................................... 1340
27-98. SPI/MibSPI Pins During Slave Mode in 4-Pin with SPIENA Configuration...................................... 1340
27-99. SPI/MibSPI Pins During Slave Mode in 5-Pin Configuration (Single Slave)..................................... 1340
27-100. SPI/MibSPI Pins During Slave Mode in 5-Pin Configuration (Single/Multi-Slave)............................. 1340
28-1. SCI Block Diagram...................................................................................................... 1346
28-2. SCI/LIN Block Diagram................................................................................................. 1347
28-3. Typical SCI Data Frame Formats ..................................................................................... 1348
28-4. Asynchronous Communication Bit Timing ........................................................................... 1349
28-5. Superfractional Divider Example ...................................................................................... 1351
28-6. Idle-Line Multiprocessor Communication Format ................................................................... 1353
28-7. Address-Bit Multiprocessor Communication Format................................................................ 1353
28-8. Receive Buffers.......................................................................................................... 1354
28-9. Transmit Buffers......................................................................................................... 1355
28-10. General Interrupt Scheme.............................................................................................. 1356
28-11. Interrupt Generation for Given Flags ................................................................................. 1357
28-12. LIN Protocol Message Frame Format: Master Header and Slave Response................................... 1364
28-13. Header 3 Fields: Synch Break, Synch, and ID ...................................................................... 1364
28-14. Response Format of LIN Message Frame........................................................................... 1365
28-15. Message Header in Terms of T
bit
...................................................................................... 1368
28-16. ID Field ................................................................................................................... 1368
28-17. Measurements for Synchronization ................................................................................... 1370
28-18. Synchronization Validation Process and Baud Rate Adjustment ................................................. 1371
28-19. Optional Embedded Checksum in Response for Extended Frames ............................................. 1372
28-20. Checksum Compare and Send for Extended Frames.............................................................. 1373
28-21. TXRX Error Detector.................................................................................................... 1375
28-22. Classic Checksum Generation at Transmitting Node .............................................................. 1376
28-23. LIN 2.0-Compliant Checksum Generation at Transmitting Node ................................................. 1376
28-24. ID Reception, Filtering and Validation ................................................................................ 1378
56
List of Figures SPNU562–May 2014
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