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27-32. SPI Global Control Register 0 (SPIGCR0) [offset = 00h] .......................................................... 1262
27-33. SPI Global Control Register 1 (SPIGCR1) [offset = 04h] .......................................................... 1263
27-34. SPI Interrupt Register (SPIINT0) [offset = 08h] ..................................................................... 1264
27-35. SPI Interrupt Level Register (SPILVL) [offset = 0Ch]............................................................... 1266
27-36. SPI Flag Register (SPIFLG) [offset = 10h] .......................................................................... 1267
27-37. SPI Pin Control Register 0 (SPIPC0) [offset = 14h] ................................................................ 1270
27-38. SPI Pin Control Register 1 (SPIPC1) [offset = 18h] ............................................................... 1271
27-39. SPI Pin Control Register 2 (SPIPC2) [offset = 1Ch]................................................................ 1273
27-40. SPI Pin Control Register 3 (SPIPC3) [offset = 20h] ............................................................... 1274
27-41. SPI Pin Control Register 4 (SPIPC4) [offset = 24h] ............................................................... 1275
27-42. SPI Pin Control Register 5 (SPIPC5) [offset = 28h] ............................................................... 1277
27-43. SPI Pin Control Register 6 (SPIPC6) [offset = 2Ch] ............................................................... 1278
27-44. SPI Pin Control Register 7 (SPIPC7) [offset = 30h] ............................................................... 1280
27-45. SPI Pin Control Register 8 (SPIPC8) [offset = 34h] ............................................................... 1281
27-46. SPI Transmit Data Register 0 (SPIDAT0) [offset = 38h] ........................................................... 1282
27-47. SPI Transmit Data Register 1 (SPIDAT1) [offset = 3Ch]........................................................... 1283
27-48. SPI Receive Buffer Register (SPIBUF) [offset = 40h] .............................................................. 1284
27-49. SPI Emulation Register (SPIEMU) [offset = 44h] ................................................................... 1286
27-50. SPI Delay Register (SPIDELAY) [offset = 48h] ..................................................................... 1286
27-51. Example: t
C2TDELAY
= 8 VCLK Cycles................................................................................... 1288
27-52. Example: t
T2CDELAY
= 4 VCLK Cycles................................................................................... 1288
27-53. Transmit-Data-Finished-to-ENA-Inactive-Timeout .................................................................. 1288
27-54. Chip-Select-Active-to-ENA-Signal-Active-Timeout.................................................................. 1288
27-55. SPI Default Chip Select Register (SPIDEF) [offset = 4Ch] ........................................................ 1289
27-56. SPI Data Format Registers (SPIFMTn) [offset = 5Ch-50h] ........................................................ 1290
27-57. Interrupt Vector 0 (NTVECT0) [offset = 60h] ........................................................................ 1292
27-58. Interrupt Vector 1 (INTVECT1) [offset = 64h]........................................................................ 1293
27-59. Parallel/Modulo Mode Control Register (SPIPMCTRL) [offset = 6Ch] ........................................... 1294
27-60. Multi-buffer Mode Enable Register (MIBSPIE) [offset = 70h]...................................................... 1297
27-61. TG Interrupt Enable Set Register (TGITENST) [offset = 74h]..................................................... 1298
27-62. TG Interrupt Enable Clear Register (TGITENCR) [offset = 78h].................................................. 1299
27-63. Transfer Group Interrupt Level Set Register (TGITLVST) [offset = 7Ch] ........................................ 1300
27-64. Transfer Group Interrupt Level Clear Register (TGITLVCR) [offset = 80h]...................................... 1301
27-65. Transfer Group Interrupt Flag Register (TGINTFLAG) [offset = 84h] ............................................ 1302
27-66. Tick Counter Operation................................................................................................. 1303
27-67. Tick Count Register (TICKCNT) [offset = 90h] ...................................................................... 1303
27-68. Last TG End Pointer (LTGPEND) [offset = 94h] .................................................................... 1304
27-69. MibSPI TG Control Registers (TGxCTRL) [offsets = 98h-D4h] ................................................... 1305
27-70. DMA Channel Control Register (DMAxCTRL) [offset = D8h-F4h] ................................................ 1308
27-71. DMAxCOUNT Register (ICOUNT) [offset = F8h-114h] ............................................................ 1310
27-72. DMA Large Count Register (DMACNTLEN) [offset = 118h]....................................................... 1311
27-73. Parity/ECC Control Register (PAR_ECC_CTRL) [offset = 120]................................................... 1312
27-74. Parity/ECC Status Register (PAR_ECC_STAT) [offset = 124].................................................... 1313
27-75. Uncorrectable Parity or Double Bit ECC Error Address Register - RXRAM (UERRADDR1) [offset =
128h] ...................................................................................................................... 1314
27-76. Uncorrectable Parity or Double Bit ECC Error Address Register - TXRAM (UERRADDR0) [offset =
12Ch]...................................................................................................................... 1316
27-77. RXRAM Overrun Buffer Address Register (RXOVRN_BUF_ADDR) [offset = 130h]........................... 1317
27-78. I/O-Loopback Test Control Register (IOLPBKTSTCR) [offset = 134h]........................................... 1318
55
SPNU562–May 2014 List of Figures
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