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26-62. IF1 Message Control Register (DCAN IF1MCTL) [offset = 10Ch] ................................................ 1210

26-63. IF2 Message Control Register (DCAN IF2MCTL) [offset = 12Ch] ................................................ 1210

26-64. IF1 Data A Register (DCAN IF1DATA) [offset = 110h]............................................................. 1212

26-65. IF1 Data B Register (DCAN IF1DATB) [offset = 114h]............................................................. 1212

26-66. IF2 Data A Register (DCAN IF2DATA) [offset = 130h]............................................................. 1212

26-67. IF2 Data B Register (DCAN IF2DATB) [offset = 134h]............................................................. 1212

26-68. IF3 Observation Register (DCAN IF3OBS) [offset = 140h] ........................................................ 1213

26-69. IF3 Mask Register (DCAN IF3MSK) [offset = 144h]................................................................ 1215

26-70. IF3 Arbitration Register (DCAN IF3ARB) [offset = 148h] .......................................................... 1216

26-71. IF3 Message Control Register (DCAN IF3MCTL) [offset = 14Ch] ............................................... 1217

26-72. IF3 Data A Register (DCAN IF3DATA) [offset = 150h]............................................................. 1218

26-73. IF3 Data B Register (DCAN IF3DATB) [offset = 154h]............................................................. 1218

26-74. IF3 Update Enable 12 Register (DCAN IF3UPD12) [offset = 160h].............................................. 1219

26-75. IF3 Update Enable 34 Register (DCAN IF3UPD34) [offset = 164h].............................................. 1219

26-76. IF3 Update Enable 56 Register (DCAN IF3UPD56) [offset = 168h].............................................. 1219

26-77. IF3 Update Enable 78 Register (DCAN IF3UPD78) [offset = 16Ch] ............................................. 1219

26-78. CAN TX IO Control Register (DCAN TIOC) [offset = 1E0h]....................................................... 1220

26-79. CAN RX IO Control Register (DCAN RIOC) [offset = 1E4h] ...................................................... 1221

27-1. SPI Functional Logic Diagram ......................................................................................... 1227

27-2. MibSPI Functional Logic Diagram..................................................................................... 1228

27-3. DMA Channel and Request Line (Logical) Structure in Multi-buffer Mode ...................................... 1230

27-4. TG Interrupt Structure .................................................................................................. 1232

27-5. SPIFLG Interrupt Structure............................................................................................. 1232

27-6. SPI Three-Pin Operation .............................................................................................. 1233

27-7. Operation with SPISCS................................................................................................. 1234

27-8. Operation with SPIENA................................................................................................. 1235

27-9. SPI Five-Pin Option with SPIENA and SPISCS..................................................................... 1236

27-10. Format for Transmitting an 8-Bit Word ............................................................................... 1237

27-11. Format for Receiving an 8-Bit Word .................................................................................. 1237

27-12. Clock Mode with Polarity = 0 and Phase = 0........................................................................ 1238

27-13. Clock Mode with Polarity = 0 and Phase = 1........................................................................ 1238

27-14. Clock Mode with Polarity = 1 and Phase = 0........................................................................ 1239

27-15. Clock Mode with Polarity = 1 and Phase = 1........................................................................ 1239

27-16. Five Bits per Character (5-Pin Option) ............................................................................... 1240

27-17. Example: t

C2TDELAY

= 8 VCLK Cycles................................................................................... 1241

27-18. Example: t

T2CDELAY

= 4 VCLK Cycles................................................................................... 1242

27-19. Transmit-Data-Finished-to-ENA-Inactive-Timeout .................................................................. 1242

27-20. Chip-Select-Active-to-ENA-Signal-Active-Timeout.................................................................. 1243

27-21. Typical Diagram when a Buffer in Master is in CSHOLD Mode (SPI-SPI) ...................................... 1244

27-22. Block Diagram Shift Register, MSB First............................................................................. 1246

27-23. Block Diagram Shift Register, LSB First ............................................................................. 1246

27-24. 2-data Line Mode (Phase 0, Polarity 0) .............................................................................. 1249

27-25. Two-Pin Parallel Mode Timing Diagram (Phase 0, Polarity 0) .................................................... 1249

27-26. 4-Data Line Mode (Phase 0, Polarity 0).............................................................................. 1250

27-27. 4 Pins Parallel Mode Timing Diagram (Phase 0, Polarity 0)....................................................... 1250

27-28. Eight-data Line Mode (Phase 0, Polarity 0).......................................................................... 1251

27-29. 8 Pins Parallel Mode Timing Diagram (Phase 0, Polarity 0)....................................................... 1252

27-30. Multi-buffer in Slave Mode ............................................................................................. 1253

27-31. I/O Paths During I/O Loopback Modes............................................................................... 1258

List of Figures SPNU562–May 2014

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