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26-13. CAN Interrupt Topology 1 .............................................................................................. 1171
26-14. CAN Interrupt Topology 2 .............................................................................................. 1172
26-15. Local Power Down Mode Flow Diagram ............................................................................. 1174
26-16. CAN Core in Silent Mode .............................................................................................. 1175
26-17. CAN Core in Loop Back Mode ........................................................................................ 1176
26-18. CAN Core in External Loop Back Mode.............................................................................. 1177
26-19. CAN Core in Loop Back Combined with Silent Mode .............................................................. 1178
26-20. CAN Control Register (DCAN CTL) [offset = 00h] .................................................................. 1182
26-21. Error and Status Register (DCAN ES) [offset = 04h] ............................................................... 1185
26-22. Error Counter Register (DCAN ERRC) [offset = 08h] .............................................................. 1187
26-23. Bit Timing Register (DCAN BTR) [offset = 0Ch] .................................................................... 1188
26-24. Interrupt Register (DCAN INT) [offset = 10h]........................................................................ 1189
26-25. Test Register (DCAN TEST) [offset = 14h] .......................................................................... 1190
26-26. Parity Error Code Register (DCAN PERR) [offset = 1Ch] ......................................................... 1191
26-27. ECC Diagnostic Register (DCAN ECCDIAG) [offset = 24h] ....................................................... 1191
26-28. ECC Diagnostic Status Register (DCAN ECCDIAG STAT) [offset = 28h]....................................... 1192
26-29. ECC Control and Status Register (DCAN ECC CS) [offset = 2Ch]............................................... 1193
26-30. ECC Single Bit Error Code Register (DCAN ECC SERR) [offset = 30h] ........................................ 1194
26-31. Auto-Bus-On Time Register (DCAN ABOTR) [offset = 80h]....................................................... 1195
26-32. Transmission Request X Register (DCAN TXRQ X) [offset = 84h]............................................... 1195
26-33. Transmission Request 12 Register (DCAN TXRQ12) [offset = 88h] ............................................. 1196
26-34. Transmission Request 34 Register (DCAN TXRQ34) [offset = 8Ch]............................................. 1196
26-35. Transmission Request 56 Register (DCAN TXRQ56) [offset = 90h] ............................................. 1196
26-36. Transmission Request 78 Register (DCAN TXRQ78) [offset = 94h] ............................................. 1196
26-37. New Data X Register (DCAN NWDAT X) [offset = 98h] ........................................................... 1197
26-38. New Data 12 Register (DCAN NWDAT12) [offset = 9Ch] ......................................................... 1198
26-39. New Data 34 Register (DCAN NWDAT34) [offset = A0h] ......................................................... 1198
26-40. New Data 56 Register (DCAN NWDAT56) [offset = A4h] ......................................................... 1198
26-41. New Data 78 Register (DCAN NWDAT78) [offset = A8h] ......................................................... 1198
26-42. Interrupt Pending X Register (DCAN INTPND X) [offset = ACh] ................................................. 1199
26-43. Interrupt Pending 12 Register (DCAN INTPND12) [offset = B0h] ................................................ 1200
26-44. Interrupt Pending 34 Register (DCAN INTPND34) [offset = B4h] ................................................ 1200
26-45. Interrupt Pending 56 Register (DCAN INTPND56) [offset = B8h] ................................................ 1200
26-46. Interrupt Pending 78 Register (DCAN INTPND78) [offset = BCh] ................................................ 1200
26-47. Message Valid X Register (DCAN MSGVAL X) [offset = C0h].................................................... 1201
26-48. Message Valid 12 Register (DCAN MSGVAL12) [offset = C4h] .................................................. 1202
26-49. Message Valid 34 Register (DCAN MSGVAL34) [offset = C8h] .................................................. 1202
26-50. Message Valid 56 Register (DCAN MSGVAL56) [offset = CCh].................................................. 1202
26-51. Message Valid 78 Register (DCAN MSGVAL78) [offset = D0h] .................................................. 1202
26-52. Interrupt Multiplexer 12 Register (DCAN INTMUX12) [offset = D8h]............................................. 1203
26-53. Interrupt Multiplexer 34 Register (DCAN INTMUX34) [offset = DCh] ............................................ 1203
26-54. Interrupt Multiplexer 56 Register (DCAN INTMUX56) [offset = E0h] ............................................. 1203
26-55. Interrupt Multiplexer 78 Register (DCAN INTMUX78) [offset = E4h] ............................................. 1203
26-56. IF1 Command Registers (DCAN IF1CMD) [offset = 100h] ........................................................ 1204
26-57. IF2 Command Registers (DCAN IF2CMD) [offset = 120h] ........................................................ 1204
26-58. IF1 Mask Register (DCAN IF1MSK) [offset = 104h]................................................................ 1207
26-59. IF2 Mask Register (DCAN IF2MSK) [offset = 124h]................................................................ 1207
26-60. IF1 Arbitration Register (DCAN IF1ARB) [offset = 108h] .......................................................... 1208
26-61. IF2 Arbitration Register (DCAN IF2ARB) [offset = 128h] .......................................................... 1208
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SPNU562–May 2014 List of Figures
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