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24-36. Module Identification Register (HTU ID) [offset = 60h]............................................................. 1101
24-37. Parity Control Register (HTU PCR) [offset = 64h] .................................................................. 1102
24-38. Parity Address Register (HTU PAR) [offset = 68h] ................................................................. 1103
24-39. Memory Protection Control and Status Register (HTU MPCS) [offset = 70h]................................... 1104
24-40. Memory Protection Start Address Register 0 (HTU MP0S) [offset = 74h]....................................... 1107
24-41. Memory Protection End Address Register (HTU MP0E) [offset = 78h] .......................................... 1107
24-42. Initial Full Address A Register (HTU IFADDRA) .................................................................... 1109
24-43. Initial Full Address B Register (HTU IFADDRB) .................................................................... 1109
24-44. Initial NHET Address and Control Register (HTU IHADDRCT) ................................................... 1110
24-45. Initial Transfer Count Register (HTU ITCOUNT).................................................................... 1111
24-46. Current Full Address A Register (HTU CFADDRA) ................................................................ 1112
24-47. Current Full Address B Register (HTU CFADDRB) ................................................................ 1113
24-48. Current Frame Count Register (HTU CFCOUNT) .................................................................. 1114
25-1. GIO Block Diagram ..................................................................................................... 1118
25-2. I/O Function Quick Start Flow Chart.................................................................................. 1119
25-3. Interrupt Generation Function Quick Start Flow Chart ............................................................. 1120
25-4. GIO Block Diagram ..................................................................................................... 1122
25-5. GIO Global Control Register (GIOGCR0) [offset = 00h] ........................................................... 1125
25-6. GIO Interrupt Detect Register (GIOINTDET) [offset = 08h]........................................................ 1126
25-7. GIO Interrupt Polarity Register (GIOPOL) [offset = 0Ch] .......................................................... 1127
25-8. GIO Interrupt Enable Set Register (GIOENASET) [offset = 10h] ................................................. 1128
25-9. GIO Interrupt Enable Clear Register (GIOENACLR) [offset = 14h]............................................... 1129
25-10. GIO Interrupt Priority Register (GIOLVLSET) [offset = 18h]....................................................... 1130
25-11. GIO Interrupt Priority Register (GIOLVLCLR) [offset = 1Ch] ...................................................... 1132
25-12. GIO Interrupt Flag Register (GIOFLG) [offset = 20h]............................................................... 1133
25-13. GIO Offset 1 Register (GIOOFF1) [offset = 24h].................................................................... 1134
25-14. GIO Offset 2 Register (GIOOFF2) [offset = 28h].................................................................... 1135
25-15. GIO Emulation 1 Register (GIOEMU1) [offset = 2Ch].............................................................. 1136
25-16. GIO Emulation 2 Register (GIOEMU2) [offset = 30h] .............................................................. 1137
25-17. GIO Data Direction Registers (GIODIR[A-B]) [offset = 34h, 54h]................................................. 1138
25-18. GIO Data Input Registers (GIODIN[A-B]) [offset = 38h, 58h] ..................................................... 1138
25-19. GIO Data Output Registers (GIODOUT[A-B]) [offset = 3Ch, 5Ch] ............................................... 1139
25-20. GIO Data Set Registers (GIODSET[A-B]) [offset = 40h, 60h]..................................................... 1139
25-21. GIO Data Clear Registers (GIODCLR[A-B]) [offset = 44h, 64h] .................................................. 1140
25-22. GIO Open Drain Registers (GIOPDR[A-B]) [offset = 48h, 68h] ................................................... 1140
25-23. GIO Pull Disable Registers (GIOPULDIS[A-B]) [offset = 4Ch, 6Ch].............................................. 1141
25-24. GIO Pull Select Registers (GIOPSL[A-B]) [offset = 50h, 70h]..................................................... 1141
26-1. DCAN Block Diagram................................................................................................... 1145
26-2. Bit Timing................................................................................................................. 1147
26-3. CAN Bit-timing Configuration .......................................................................................... 1152
26-4. Structure of a Message Object ........................................................................................ 1154
26-5. Message RAM Representation in Debug/Suspend Mode ......................................................... 1157
26-6. Message RAM Representation in RAM Direct Access Mode ..................................................... 1157
26-7. ECC RAM Representation ............................................................................................. 1158
26-8. Data Transfer Between IF1 / IF2 Registers and Message RAM.................................................. 1160
26-9. Initialization of a Transmit Object ..................................................................................... 1162
26-10. Initialization of a Single Receive Object for Data Frames ......................................................... 1162
26-11. Initialization of a Single Receive Object for Remote Frames...................................................... 1163
26-12. CPU Handling of a FIFO Buffer (Interrupt Driven) .................................................................. 1168
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List of Figures SPNU562–May 2014
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