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22-99. ADC Power-Up Delay Control Register (ADPWRUPDLYCTRL) [offset = 188h] ................................. 923
22-100. ADC Event Group Channel Selection Mode Control Register (ADEVCHNSELMODECTRL) (offset =
190h) ....................................................................................................................... 924
22-101. ADC Group1 Channel Selection Mode Control Register (ADG1CHNSELMODECTRL) (offset = 194h) .... 924
22-102. ADC Group2 Channel Selection Mode Control Register (ADG1CHNSELMODECTRL) (offset = 198h) .... 925
22-103. ADC Event Group Current Count Register (ADEVCURRCOUNT) (offset = 19Ch) ............................ 926
22-104. ADC Event Group Maximum Count Register (ADEVMAXCOUNT) (offset = 1A0h)............................ 926
22-105. ADC Group1 Current Count Register (ADG1CURRCOUNT) (offset = 1A4h)................................... 927
22-106. ADC Group1 Maximum Count Register (ADG1MAXCOUNT) (offset = 1A8h) .................................. 927
22-107. ADC Group2 Current Count Register (ADG2CURRCOUNT) (offset = 1ACh) .................................. 928
22-108. ADC Group2 Maximum Count Register (ADG2MAXCOUNT) (offset = 1B0h) .................................. 928
23-1. N2HET Block Diagram ................................................................................................... 934
23-2. Specialized Timer Micromachine ....................................................................................... 935
23-3. Program Flow Timings ................................................................................................... 936
23-4. Use of the Overflow Interrupt Flag (HETEXC2) ...................................................................... 937
23-5. Multi-Resolution Operation Flow Example ............................................................................ 938
23-6. Debug Control Configuration............................................................................................ 939
23-7. Prescaler Configuration .................................................................................................. 942
23-8. I/O Control ................................................................................................................. 946
23-9. N2HET Loop Resolution Structure for Each Bit ...................................................................... 947
23-10. Loop Resolution Instruction Execution Example ..................................................................... 947
23-11. HR I/O Architecture....................................................................................................... 948
23-12. Example of HR Structure Sharing for N2HET Pins 0/1 .............................................................. 949
23-13. XOR-shared HR I/O ...................................................................................................... 949
23-14. Symmetrical PWM with XOR-sharing Output ......................................................................... 950
23-15. AND-shared HR I/O ...................................................................................................... 951
23-16. HR0 to HR1 Digital Loopback Logic: LBTYPE[0] = 0 ................................................................ 952
23-17. HR0 to HR1 Analog Loop Back Logic: LBTYPE[0] = 1 .............................................................. 952
23-18. N2HET Input Edge Detection ........................................................................................... 953
23-19. ECMP Execution Timings................................................................................................ 954
23-20. High/Low Resolution Modes for ECMP and PWCNT ................................................................ 955
23-21. PCNT Instruction Timing (With Capture Edge After HR Counter Overflow) ...................................... 956
23-22. PCNT Instruction Timing (With Capture Edge Before HR Counter Overflow) .................................... 956
23-23. WCAP Instruction Timing ................................................................................................ 957
23-24. I/O Block Diagram Including Pull Control Logic....................................................................... 957
23-25. N2HET Pin Disable Feature Diagram.................................................................................. 959
23-26. Suppression Filter Counter Operation ................................................................................. 960
23-27. Interrupt Functionality on Instruction Level ............................................................................ 961
23-28. Interrupt Flag/Priority Level Architecture............................................................................... 962
23-29. Request Line Assignment Example .................................................................................... 963
23-30. Operation of N2HET Count Instructions ............................................................................... 964
23-31. SCNT Count Operation .................................................................................................. 965
23-32. ACNT Period Variation Compensations ............................................................................... 965
23-33. N2HET Timings Associated with the Gap Flag (ACNT Deceleration) ............................................. 966
23-34. N2HET Timings Associated with the Gap Flag (ACNT Acceleration) ............................................. 966
23-35. Global Configuration Register (HETGCR)............................................................................. 969
23-36. Prescale Factor Register (HETPFR) ................................................................................... 970
23-37. N2HET Current Address (HETADDR) ................................................................................. 971
23-38. Offset Index Priority Level 1 Register (HETOFF1) ................................................................... 971
48
List of Figures SPNU562–May 2014
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