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22-50. ADC Event Group Status Register (ADEVSR) [offset = 6Ch] ...................................................... 893
22-51. ADC Group1 Status Register (ADG1SR) [offset = 70h] ............................................................. 894
22-52. ADC Group2 Status Register (ADG2SR) [offset = 74h] ............................................................. 895
22-53. ADC Event Group Channel Select Register (ADEVSEL) [offset = 78h]........................................... 896
22-54. ADC Group1 Channel Select Register (ADG1SEL) [offset = 7Ch]................................................. 897
22-55. ADC Group2 Channel Select Register (ADG2SEL) [offset = 80h] ................................................. 898
22-56. 12-bit ADC Calibration and Error Offset Correction Register (ADCALR) [offset = 84h]......................... 899
22-57. 10-bit ADC Calibration and Error Offset Correction Register (ADCALR) [offset = 84h]......................... 899
22-58. ADC State Machine Status Register (ADSMSTATE) [offset = 88h] ............................................... 899
22-59. ADC Channel Last Conversion Value Register (ADLASTCONV) [offset = 8Ch]................................. 900
22-60. 12-bit ADC Event Group Results' FIFO Register (ADEVBUFFER) [offset = 90h-AFh].......................... 901
22-61. 10-bit ADC Event Group Results' FIFO Register (ADEVBUFFER) [offset = 90h-AFh].......................... 901
22-62. 12-bit ADC Group1 Results FIFO Register (ADG1BUFFER) [offset = B0h-CFh] ................................ 902
22-63. 10-bit ADC Group1 Results' FIFO Register (ADG1BUFFER) [offset = B0h-CFh] ............................... 902
22-64. 12-bit ADC Group2 Results FIFO Register (ADG2BUFFER) [offset = D0h-EFh] ................................ 903
22-65. 10-bit ADC Group2 Results' FIFO Register (ADG2BUFFER) [offset = D0h-EFh] ............................... 903
22-66. 12-bit ADC Event Group Results Emulation FIFO Register (ADEVEMUBUFFER) [offset = F0h] ............. 904
22-67. 10-bit ADC Event Group Results Emulation FIFO Register (ADEVEMUBUFFER) [offset = F0h] ............. 904
22-68. 12-bit ADC Group1 Results Emulation FIFO Register (ADG1EMUBUFFER) [offset = F4h] ................... 905
22-69. 10-bit ADC Group1 Results Emulation FIFO Register (ADG1EMUBUFFER) [offset = F4h] ................... 905
22-70. 12-bit ADC Group2 Results Emulation FIFO Register (ADG2EMUBUFFER) [offset = F8h] ................... 906
22-71. 10-bit ADC Group2 Results Emulation FIFO Register (ADG2EMUBUFFER) [offset = F8h] ................... 906
22-72. ADC ADEVT Pin Direction Control Register (ADEVTDIR) [offset = FCh]......................................... 907
22-73. ADC ADEVT Pin Output Value Control Register (ADEVTOUT) [offset = 100h].................................. 908
22-74. ADC ADEVT Pin Input Value Register (ADEVTIN) [offset = 104h] ................................................ 908
22-75. ADC ADEVT Pin Set Register (ADEVTSET) [offset = 108h] ....................................................... 909
22-76. ADC ADEVT Pin Clear Register (ADEVTCLR) [offset = 10Ch] .................................................... 909
22-77. ADC ADEVT Pin Open Drain Enable Register (ADEVTPDR) [offset = 110h].................................... 910
22-78. ADC ADEVT Pin Pull Control Disable Register (ADEVTPDIS) [offset = 114h]................................... 910
22-79. ADC ADEVT Pin Pull Control Select Register (ADEVTPSEL) [offset = 118h] ................................... 911
22-80. ADC Event Group Sample Cap Discharge Control Register (ADEVSAMPDISEN) [offset = 11Ch] ........... 911
22-81. ADC Group1 Sample Cap Discharge Control Register (ADG1SAMPDISEN) [offset = 120h].................. 912
22-82. ADC Group2 Sample Cap Discharge Control Register (ADG2SAMPDISEN) [offset = 124h].................. 913
22-83. 12-bit ADC Magnitude Compare Interrupt Control Registers (ADMAGINTxCR) [offset = 128h-138h] ........ 914
22-84. 10-bit ADC Magnitude Compare Interrupt Control Registers (ADMAGINTxCR) [offset = 128h-138h] ........ 914
22-85. 12-bit ADC Magnitude Compare Mask Register (ADMAGINTxMASK) [offset = 12Ch-13Ch].................. 916
22-86. 10-bit ADC Magnitude Compare Mask Register (ADMAGINTxMASK) [offset = 12Ch-13Ch].................. 916
22-87. ADC Magnitude Compare Interrupt Enable Set Register (ADMAGINTENASET) [offset = 158h].............. 917
22-88. ADC Magnitude Compare Interrupt Enable Clear Register (ADMAGINTENACLR) [offset = 15Ch]........... 917
22-89. ADC Magnitude Compare Interrupt Flag Register (ADMAGINTFLG) [offset = 160h] ........................... 918
22-90. ADC Magnitude Compare Interrupt Offset Register (ADMAGINTOFF) [offset = 164h] ......................... 918
22-91. ADC Event Group FIFO Reset Control Register (ADEVFIFORESETCR) [offset = 168h] ...................... 919
22-92. ADC Group1 FIFO Reset Control Register (ADG1FIFORESETCR) [offset = 16Ch] ............................ 919
22-93. ADC Group2 FIFO Reset Control Register (ADG2FIFORESETCR) [offset = 170h]............................. 920
22-94. ADC Event Group RAM Write Address Register (ADEVRAMWRADDR) [offset = 174h]....................... 920
22-95. ADC Group1 RAM Write Address Register (ADG1RAMWRADDR) [offset = 178h] ............................. 921
22-96. ADC Group2 RAM Write Address Register (ADG2RAMWRADDR) [offset = 17Ch]............................. 921
22-97. ADC Parity Control Register (ADPARCR) [offset = 180h]........................................................... 922
22-98. ADC Parity Error Address Register (ADPARADDR) [offset = 184h]............................................... 923
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SPNU562–May 2014 List of Figures
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