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22-1. Channel Assignments of Two ADC Cores ............................................................................ 826
22-2. ADC Block Diagram ..................................................................................................... 827
22-3. FIFO Implementation .................................................................................................... 831
22-4. Format of Conversion Result Read from FIFO, 12-bit ADC......................................................... 832
22-5. Format of Conversion Result Read from FIFO, 10-bit ADC......................................................... 832
22-6. ADC Memory Mapping .................................................................................................. 833
22-7. Format of Conversion Result Directly Read from ADC RAM, 12-bit ADC ........................................ 833
22-8. Format of Conversion Result Directly Read from ADC RAM, 10-bit ADC ........................................ 833
22-9. Conversion Results Storage ............................................................................................ 834
22-10. ADC Groups’ Operating Mode Control and Status Registers....................................................... 836
22-11. Example Look-Up Table Entry .......................................................................................... 838
22-12. Group1 Enhanced Channel Selection Mode Example............................................................... 839
22-13. Self-Test and Calibration Logic ......................................................................................... 847
22-14. Mid-point Value Calculation ............................................................................................. 850
22-15. Self-Test and Calibration Logic ......................................................................................... 851
22-16. Timing for Self-Test Mode ............................................................................................... 852
22-17. Timing for Sample Capacitor Discharge Mode ....................................................................... 853
22-18. ADC Memory Map in Parity Test Mode................................................................................ 855
22-19. GPIO Functionality of ADxEVT ......................................................................................... 855
22-20. ADC Reset Control Register (ADRSTCR) [offset = 00].............................................................. 859
22-21. ADC Operating Mode Control Register (ADOPMODECR) [offset = 04]........................................... 859
22-22. ADC Clock Control Register (ADCLOCKCR) [offset = 08h]......................................................... 861
22-23. ADC Calibration Mode Control Register (ADCALCR) [offset = 0Ch] .............................................. 861
22-24. 12-bit ADC Event Group Operating Mode Control Register (ADEVMODECR) [offset = 10h].................. 863
22-25. 10-bit ADC Event Group Operating Mode Control Register (ADEVMODECR) [offset = 10h].................. 863
22-26. 12-bit ADC Group1 Operating Mode Control Register (ADG1MODECR) [offset = 14h] ........................ 866
22-27. 10-bit ADC Group1 Operating Mode Control Register (ADG1MODECR) [offset = 14h] ........................ 866
22-28. 12-bit ADC Group2 Operating Mode Control Register (ADG2MODECR) [offset = 18h] ........................ 869
22-29. 10-bit ADC Group2 Operating Mode Control Register (ADG2MODECR) [offset = 18h] ........................ 869
22-30. ADC Event Group Trigger Source Select Register (ADEVSRC) [offset = 1Ch] .................................. 872
22-31. ADC Group1 Trigger Source Select Register (ADG1SRC) [offset = 20h]......................................... 873
22-32. ADC Group2 Trigger Source Select Register (ADG2SRC) [offset = 24h]......................................... 874
22-33. ADC Event Group Interrupt Enable Control Register (ADEVINTENA) [offset = 28h]............................ 875
22-34. ADC Group1 Interrupt Enable Control Register (ADG1INTENA) [offset = 2Ch] ................................. 876
22-35. ADC Group2 Interrupt Enable Control Register (ADG2INTENA) [offset = 30h].................................. 877
22-36. ADC Event Group Interrupt Flag Register (ADEVINTFLG) [offset = 34h]......................................... 878
22-37. ADC Group1 Interrupt Flag Register (ADG1INTFLG) [offset = 38h]............................................... 879
22-38. ADC Group2 Interrupt Flag Register (ADG2INTFLG) [offset = 3Ch] .............................................. 880
22-39. ADC Event Group Threshold Interrupt Control Register (ADEVTHRINTCR) [offset = 40h] .................... 881
22-40. ADC Group1 Threshold Interrupt Control Register (ADG1THRINTCR) [offset = 44h] .......................... 881
22-41. ADC Group2 Threshold Interrupt Control Register (ADG2THRINTCR) [offset = 48h] .......................... 882
22-42. ADC Event Group DMA Control Register (ADEVDMACR) [offset = 4Ch]......................................... 883
22-43. ADC Group1 DMA Control Register (ADG1DMACR) [offset = 50h] ............................................... 885
22-44. ADC Group2 DMA Control Register (ADG2DMACR) [offset = 54h] ............................................... 887
22-45. ADC Results Memory Configuration Register (ADBNDCR) [offset = 58h] ........................................ 889
22-46. ADC Results Memory Size Configuration Register (ADBNDEND) [offset = 5Ch]................................ 890
22-47. ADC Event Group Sampling Time Configuration Register (ADEVSAMP) [offset = 60h]........................ 891
22-48. ADC Group1 Sampling Time Configuration Register (ADG1SAMP) [offset = 64h] .............................. 891
22-49. ADC Group2 Sampling Time Configuration Register (ADG2SAMP) [offset = 68h] .............................. 892
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List of Figures SPNU562–May 2014
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