Datasheet

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20-106. DMA ECC Single Bit Error Address Register (DMAECCSBE) [offset = 230h] .................................. 759
20-107. FIFO A Status Register (FIFOASTAT) [offset = 240h] ............................................................. 760
20-108. FIFO B Status Register (FIFOBSTAT) [offset = 244h] ............................................................. 760
20-109. DMA Request Polarity Select Register (DMAREQPS1) [offset = 330h] ......................................... 761
20-110. DMA Request Polarity Select Register (DMAREQPS0) [offset = 334h] ......................................... 761
20-111. Transaction Parity Error Event Control Register (TERECTRL) [offset = 340h] ................................. 762
20-112. TER Event Flag Register (TERFLAG) [offset = 344h].............................................................. 762
20-113. TER Event Channel Offset Register (TERROFFSET) [offset = 348h] ........................................... 763
20-114. Initial Source Address Register (ISADDR) [offset = 00]............................................................ 764
20-115. Initial Destination Address Register (IDADDR) [offset = 04h] ..................................................... 764
20-116. Initial Transfer Count Register (ITCOUNT) [offset = 08h].......................................................... 765
20-117. Channel Control Register (CHCTRL) [offset = 10h] ................................................................ 765
20-118. Element Index Offset Register (EIOFF) [offset = 14h].............................................................. 767
20-119. Frame Index Offset Register (FIOFF) [offset = 18h]................................................................ 767
20-120. Current Source Address Register (CSADDR) [offset = 800h] ..................................................... 768
20-121. Current Destination Address Register (CDADDR) [offset = 804h]................................................ 768
20-122. Current Transfer Count Register (CTCOUNT) [offset = 808h] .................................................... 768
21-1. EMIF Functional Block Diagram ........................................................................................ 771
21-2. Timing Waveform of SDRAM PRE Command........................................................................ 775
21-3. EMIF to 2M × 16 × 4 bank SDRAM Interface......................................................................... 775
21-4. EMIF to 512K × 16 × 2 bank SDRAM Interface ...................................................................... 776
21-5. Timing Waveform for Basic SDRAM Read Operation ............................................................... 783
21-6. Timing Waveform for Basic SDRAM Write Operation ............................................................... 784
21-7. EMIF Asynchronous Interface........................................................................................... 786
21-8. EMIF to 8-bit/16-bit Memory Interface ................................................................................. 787
21-9. Common Asynchronous Interface ...................................................................................... 787
21-10. Timing Waveform of an Asynchronous Read Cycle in Normal Mode.............................................. 791
21-11. Timing Waveform of an Asynchronous Write Cycle in Normal Mode.............................................. 793
21-12. Timing Waveform of an Asynchronous Read Cycle in Select Strobe Mode ...................................... 795
21-13. Timing Waveform of an Asynchronous Write Cycle in Select Strobe Mode ...................................... 797
21-14. Asynchronous Read in Page Mode .................................................................................... 798
21-15. Module ID Register (MIDR) [offset = 00] .............................................................................. 804
21-16. Asynchronous Wait Cycle Configuration Register (AWCCR) [offset = 04h] ...................................... 805
21-17. SDRAM Configuration Register (SDCR) [offset = 08h] .............................................................. 806
21-18. SDRAM Refresh Control Register (SDRCR) [offset = 0Ch]......................................................... 807
21-19. Asynchronous n Configuration Register (CEnCFG) [offset = 10h - 1Ch].......................................... 808
21-20. SDRAM Timing Register (SDTIMR) [offset = 20h] ................................................................... 809
21-21. SDRAM Self Refresh Exit Timing Register (SDSRETR) [offset = 3Ch] ........................................... 810
21-22. EMIF Interrupt Raw Register (INTRAW) [offset = 40h] .............................................................. 811
21-23. EMIF Interrupt Mask Register (INTMSK) [offset = 44h] ............................................................. 812
21-24. EMIF Interrupt Mask Set Register (INTMSKSET) [offset = 48h] ................................................... 813
21-25. EMIF Interrupt Mask Clear Register (INTMSKCLR) [offset = 4Ch] ................................................ 814
21-26. Page Mode Control Register (PMCR) [offset = 68h] ................................................................. 815
21-27. Example Configuration Interface........................................................................................ 817
21-28. SDRAM Timing Register (SDTIMR).................................................................................... 818
21-29. SDRAM Self Refresh Exit Timing Register (SDSRETR) ............................................................ 819
21-30. SDRAM Refresh Control Register (SDRCR).......................................................................... 819
21-31. SDRAM Configuration Register (SDCR)............................................................................... 820
21-32. Asynchronous m Configuration Register (m = 1, 2) (CEnCFG (n = 2, 3)) ........................................ 824
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SPNU562–May 2014 List of Figures
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