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20-57. FTC Interrupt Flag Register (FTCFLAG) [offset = 124h] ............................................................ 728
20-58. LFS Interrupt Flag Register (LFSFLAG) [offset = 12Ch] ............................................................ 729
20-59. HBC Interrupt Flag Register (HBCFLAG) [offset = 134h] ........................................................... 729
20-60. BTC Interrupt Flag Register (BTCFLAG) [offset = 13Ch]............................................................ 730
20-61. BER Interrupt Flag Register (BERFLAG) [offset = 144h]............................................................ 730
20-62. FTCA Interrupt Channel Offset Register (FTCAOFFSET) [offset = 14Ch]........................................ 731
20-63. LFSA Interrupt Channel Offset Register (LFSAOFFSET) [offset = 150h]......................................... 731
20-64. HBCA Interrupt Channel Offset Register (HBCAOFFSET) [offset = 154h] ....................................... 732
20-65. BTCA Interrupt Channel Offset Register (BTCAOFFSET) [offset = 158h] ........................................ 732
20-66. BERA Interrupt Channel Offset Register (BERAOFFSET) [offset = 15Ch] ....................................... 733
20-67. FTCB Interrupt Channel Offset Register (FTCBOFFSET) [offset = 160h] ........................................ 733
20-68. LFSB Interrupt Channel Offset Register (LFSBOFFSET) [offset = 164h]......................................... 734
20-69. HBCB Interrupt Channel Offset Register (HBCBOFFSET) [offset = 168h] ....................................... 734
20-70. BTCB Interrupt Channel Offset Register (BTCBOFFSET) [offset = 16Ch]........................................ 735
20-71. BERB Interrupt Channel Offset Register (BERBOFFSET) [offset = 170h]........................................ 735
20-72. Port Control Register (PTCRL) [offset = 178h] ....................................................................... 736
20-73. RAM Test Control Register (RTCTRL) [offset = 17Ch] .............................................................. 737
20-74. Debug Control Register (DCTRL) [offset = 180h] .................................................................... 738
20-75. Watch Point Register (WPR) [offset = 184h].......................................................................... 739
20-76. Watch Mask Register (WMR) [offset = 188h] ......................................................................... 739
20-77. FIFO A Active Channel Source Address Register (FAACSADDR) [offset = 18ch] .............................. 740
20-78. FIFO A Active Channel Destination Address Register (FAACDADDR) [offset = 190h] ......................... 740
20-79. FIFO A Active Channel Transfer Count Register (FAACTC) [offset = 194h] ..................................... 740
20-80. FIFO B Active Channel Source Address Register (FBACSADDR) [offset = 198h] .............................. 741
20-81. FIFO B Active Channel Destination Address Register (FBACDADDR) [offset = 19Ch]......................... 741
20-82. FIFO B Active Channel Transfer Count Register (FBACTC) [offset = 1A0h] ..................................... 741
20-83. ECC Control Register (DMAPECR) [offset = 1A8h].................................................................. 742
20-84. DMA ECC Error Address Register (DMAPAR) [offset = 1ACh] .................................................... 743
20-85. DMA Memory Protection Control Register 1 (DMAMPCTRL1) [offset = 1B0h]................................... 744
20-86. DMA Memory Protection Status Register 1 (DMAMPST1) [offset = 1B4h] ....................................... 746
20-87. DMA Memory Protection Region 0 Start Address Register (DMAMPR0S) [offset = 1B8h]..................... 747
20-88. DMA Memory Protection Region 0 End Address Register (DMAMPR0E) [offset = 1BCh] ..................... 747
20-89. DMA Memory Protection Region 1 Start Address Register (DMAMPR1S) [offset = 1C0h]..................... 748
20-90. DMA Memory Protection Region 1 End Address Register (DMAMPR1E) [offset = 1C4h] ..................... 748
20-91. DMA Memory Protection Region 2 Start Address Register (DMAMPR2S) [offset = 1C8h]..................... 749
20-92. DMA Memory Protection Region 2 End Address Register (DMAMPR2E) [offset = 1CCh] ..................... 749
20-93. DMA Memory Protection Region 3 Start Address Register (DMAMPR3S) [offset = 1D0h]..................... 750
20-94. DMA Memory Protection Region 3 End Address Register (DMAMPR3E) [offset = 1D4h] ..................... 750
20-95. DMA Memory Protection Control Register 2 (DMAMPCTRL2) [offset = 1D8h] .................................. 751
20-96. DMA Memory Protection Status Register 2 (DMAMPST2) [offset = 1DCh]....................................... 753
20-97. DMA Memory Protection Region 4 Start Address Register (DMAMPR4S) [offset = 1E0h]..................... 754
20-98. DMA Memory Protection Region 4 End Address Register (DMAMPR4E) [offset = 1E4h]...................... 754
20-99. DMA Memory Protection Region 5 Start Address Register (DMAMPR5S) [offset = 1E8h]..................... 755
20-100. DMA Memory Protection Region 5 End Address Register (DMAMPR5E) [offset = 1ECh].................... 755
20-101. DMA Memory Protection Region 6 Start Address Register (DMAMPR6S) [offset = 1F0h].................... 756
20-102. DMA Memory Protection Region 6 End Address Register (DMAMPR6E) [offset = 1F4h] .................... 756
20-103. DMA Memory Protection Region 7 Start Address Register (DMAMPR7S) [offset = 1F8h].................... 757
20-104. DMA Memory Protection Region 7 End Address Register (DMAMPR7E) [offset = 1FCh] .................... 757
20-105. DMA Single Bit ECC Control Register (DMASECCCTRL) [offset = 228h]....................................... 758
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List of Figures SPNU562–May 2014
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