Datasheet

www.ti.com
15-7. DCC Control Register (DCCGCTRL) [offset = 00] ................................................................... 531
15-8. DCC Revision Id Register (DCCREV) [offset = 4h] ................................................................. 532
15-9. DCC Counter0 Seed Register (DCCCNT0SEED) [offset = 8h] .................................................... 532
15-10. DCC Valid0 Seed Register (DCCVALID0SEED) [offset = Ch] ..................................................... 533
15-11. DCC Counter1 Seed Register (DCCCNT1SEED) [offset = 10h] .................................................. 533
15-12. DCC Status Register (DCCSTAT) [offset = 14h] .................................................................... 534
15-13. DCC Counter0 Value Register (DCCCNT0) [offset = 18h] ......................................................... 535
15-14. DCC Valid0 Value Register (DCCVALID0) [offset = 1Ch] .......................................................... 536
15-15. DCC Counter1 Value Register (DCCCNT1) [offset = 20h] ......................................................... 536
15-16. DCC Counter1 Clock Source Selection Register (DCCCNT1CLKSRC) [offset = 24h] ......................... 537
15-17. DCC Counter0 Clock Source Selection Register (DCCCNT0CLKSRC) [offset = 24h] ......................... 537
16-1. Block Diagram............................................................................................................. 539
16-2. Interrupt Response Handling............................................................................................ 540
16-3. ERROR Pin Response Handling ....................................................................................... 540
16-4. ERROR Pin Timing - Example 1........................................................................................ 542
16-5. ERROR Pin Timing - Example 2........................................................................................ 542
16-6. ERROR Pin Timing - Example 3........................................................................................ 542
16-7. ERROR Pin Timing - Example 4........................................................................................ 543
16-8. ERROR Pin Timing - Example 5........................................................................................ 543
16-9. ERROR Pin Timing - Example 6........................................................................................ 543
16-10. ESM Initialization.......................................................................................................... 544
16-11. ESM Enable ERROR Pin Action/Response Register 1 (ESMEEPAPR1) [offset = 00h] ........................ 546
16-12. ESM Disable ERROR Pin Action/Response Register 1 (ESMDEPAPR1) [offset = 04h] ....................... 546
16-13. ESM Interrupt Enable Set/Status Register 1 (ESMIESR1) [offset = 08h] ......................................... 547
16-14. ESM Interrupt Enable Clear/Status Register 1 (ESMIECR1) [offset = 0Ch] ...................................... 547
16-15. ESM Interrupt Level Set/Status Register 1 (ESMILSR1) [offset = 10h] ........................................... 548
16-16. ESM Interrupt Level Clear/Status Register 1 (ESMILCR1) [offset = 14h]......................................... 548
16-17. ESM Status Register 1 (ESMSR1) [offset = 18h] .................................................................... 549
16-18. ESM Status Register 2 (ESMSR2) [offset = 1Ch] .................................................................... 549
16-19. ESM Status Register 3 (ESMSR3) [offset = 20h] .................................................................... 550
16-20. ESM ERROR Pin Status Register (ESMEPSR) [offset = 24h] ..................................................... 550
16-21. ESM Interrupt Offset High Register (ESMIOFFHR) [offset = 28h] ................................................. 551
16-22. ESM Interrupt Offset Low Register (ESMIOFFLR) [offset = 2Ch].................................................. 552
16-23. ESM Low-Time Counter Register (ESMLTCR) [offset = 30h] ...................................................... 553
16-24. ESM Low-Time Counter Preload Register (ESMLTCPR) [offset = 34h]........................................... 553
16-25. ESM Error Key Register (ESMEKR) [offset = 38h]................................................................... 554
16-26. ESM Status Shadow Register 2 (ESMSSR2) [offset = 3Ch]........................................................ 554
16-27. ESM Influence ERROR Pin Set/Status Register 4 (ESMIEPSR4) [offset = 40h] ................................ 555
16-28. ESM Influence ERROR Pin Clear/Status Register 4 (ESMIEPCR4) [offset = 44h].............................. 555
16-29. ESM Interrupt Enable Set/Status Register 4 (ESMIESR4) [offset = 48h] ......................................... 556
16-30. ESM Interrupt Enable Clear/Status Register 4 (ESMIECR4) [offset = 4Ch] ...................................... 556
16-31. ESM Interrupt Level Set/Status Register 4 (ESMILSR4) [offset = 50h] ........................................... 557
16-32. ESM Interrupt Level Clear/Status Register 4 (ESMILCR4) [offset = 54h]......................................... 557
16-33. ESM Status Register 4 (ESMSR4) [offset = 58h] .................................................................... 558
16-34. ESM Influence ERROR Pin Set/Status Register 7 (ESMIEPSR7) [offset = 80h] ................................ 559
16-35. ESM Influence ERROR Pin Clear/Status Register 7 (ESMIEPCR7) [offset = 84h].............................. 559
16-36. ESM Interrupt Enable Set/Status Register 7 (ESMIESR7) [offset = 88h] ......................................... 560
16-37. ESM Interrupt Enable Clear/Status Register 7 (ESMIECR7) [offset = 8Ch] ...................................... 560
16-38. ESM Interrupt Level Set/Status Register 7 (ESMILSR7) [offset = 90h] ........................................... 561
39
SPNU562–May 2014 List of Figures
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated