Datasheet

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9-5. PBIST Activate/ROM Clock Enable Register (PACT) [offset = 0180h] ............................................ 398
9-6. PBIST ID Register [offset = 184h] ...................................................................................... 399
9-7. Override Register (OVER) [offset = 0188h] ........................................................................... 400
9-8. Fail Status Fail Register 0 (FSRF0) [offset = 0190h] ................................................................ 401
9-9. Fail Status Fail Register 1 (FSRF1) [offset = 0194h] ................................................................ 401
9-10. Fail Status Count 0 Register (FSRC0) [offset = 0198h] ............................................................. 402
9-11. Fail Status Count Register 1 (FSRC1) [offset = 019Ch]............................................................. 402
9-12. Fail Status Address Register 0 (FSRA0) [offset = 01A0h] .......................................................... 403
9-13. Fail Status Address Register 1 (FSRA1) [offset = 01A4h] .......................................................... 403
9-14. Fail Status Data Register 0 (FSRDL0) [offset = 01A8h] ............................................................. 404
9-15. Fail Status Data Register 1 (FSRDL1) [offset = 01B0h] ............................................................. 404
9-16. ROM Mask Register (ROM) [offset = 01C0h]......................................................................... 405
9-17. ROM Algorithm Mask Register (ALGO) [offset = 01C4h]............................................................ 406
9-18. RAM Info Mask Lower Register (RINFOL) [offset = 01C8h] ........................................................ 407
9-19. RAM Info Mask Upper Register (RINFOU) [offset = 01CCh] ....................................................... 408
10-1. Block Diagram for STC With Multiple Segments ..................................................................... 414
10-2. STC1 - Segment 0 Redundant Core Architecture With CCM-R5F (Parallel Mode).............................. 415
10-3. STC2 - Segment 0 Redundant Architecture (Parallel Mode) ....................................................... 416
10-4. STC1 - Segment 0 Redundant Core Architecture With Only CPU1 Selected .................................... 417
10-5. STC1 - Segment 0 Redundant Core Architecture With Only CPU2 Selected .................................... 418
10-6. STC Programmers Flow Chart.......................................................................................... 420
10-7. Self-Test Hardware Execution Flow Chart ............................................................................ 423
10-8. STC Global Control Register 0 (STCGCR0) [offset = 00h] ......................................................... 429
10-9. STC Global Control Register 1 (STCGCR1) [offset = 04h] ......................................................... 430
10-10. Self-Test Run Timeout Counter Preload Register (STCTPR) [offset = 08h]...................................... 430
10-11. STC Current ROM Address Register (STCCADDR1) [offset = 0Ch] .............................................. 431
10-12. STC Current Interval Count Register (STCCICR) [offset = 10h] ................................................... 431
10-13. Self-Test Global Status Register (STCGSTAT) [offset = 14h] ...................................................... 432
10-14. Self-Test Fail Status Register (STCFSTAT) [offset = 18h].......................................................... 433
10-15. CORE1 Current MISR Register (CORE1_CURMISR3) [offset = 1Ch] ............................................ 434
10-16. CORE1 Current MISR Register (CORE1_CURMISR2) [offset = 20h]............................................. 434
10-17. CORE1 Current MISR Register (CORE1_CURMISR1) [offset = 24h]............................................. 434
10-18. CORE1 Current MISR Register (CORE1_CURMISR0) [offset = 28h]............................................. 434
10-19. CORE2 Current MISR Register (CORE2_CURMISR3) [offset = 2Ch] ............................................ 435
10-20. CORE2 Current MISR Register (CORE2_CURMISR2) [offset = 30h]............................................. 435
10-21. CORE2 Current MISR Register (CORE2_CURMISR1) [offset = 34h]............................................. 435
10-22. CORE2 Current MISR Register (CORE2_CURMISR0) [offset = 38h]............................................. 435
10-23. Signature Compare Self-Check Register (STCSCSCR) [offset = 3Ch] ........................................... 436
10-24. STC Current ROM Address Register (STCCADDR2) [offset = 40h]............................................... 436
10-25. STC Clock Prescalar Register (STCCLKDIV) [offset = 44h] ........................................................ 437
10-26. Segment Interval Preload Register (STCSEGPLR) [offset = 48h] ................................................. 438
11-1. NMPU Block Diagram.................................................................................................... 443
11-2. MPU Region Priority...................................................................................................... 445
11-3. Example of DMA 3 MPU Region Set Up .............................................................................. 448
11-4. MPU Revision ID Register (MPUREV) (offset = 00h)................................................................ 453
11-5. MPU Lock Register (MPULOCK) (offset = 04h) ...................................................................... 453
11-6. MPU Diagnostics Control Register (MPUDIAGCTRL) (offset = 08h) .............................................. 454
11-7. MPU Diagnostic Address Register (MPUDIAGADDR) (offset = 0Ch) ............................................. 455
11-8. MPU Error Status Register (MPUERRSTAT) (offset = 10h) ........................................................ 455
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SPNU562–May 2014 List of Figures
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