Datasheet

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5-8. Logic Power Domain PD2 Power Status Register (LOGICPDPWRSTAT0) (offset = 40h) ..................... 276
5-9. Logic Power Domain PD3 Power Status Register (LOGICPDPWRSTAT1) (offset = 44h) ..................... 277
5-10. Logic Power Domain PD4 Power Status Register (LOGICPDPWRSTAT2) (offset = 48h) ..................... 278
5-11. Logic Power Domain PD5 Power Status Register (LOGICPDPWRSTAT3) (offset = 4Ch)..................... 279
5-12. Logic Power Domain PD6 Power Status Register (LOGICPDPWRSTAT4) (offset = 50h) ..................... 280
5-13. Global Control Register 1 (GLOBALCTRL1) (offset = A0h)......................................................... 281
5-14. Global Status Register (GLOBALSTAT) (offset = A8h).............................................................. 282
5-15. PSCON Diagnostic Compare Key Register (PRCKEYREG) (offset = ACh)...................................... 282
5-16. LogicPD PSCON Diagnostic Compare Status Register 1 (LPDDCSTAT1) (offset = B0h) ..................... 283
5-17. LogicPD PSCON Diagnostic Compare Status Register 2 (LPDDCSTAT2) (offset = B4h) ..................... 284
5-18. Isolation Diagnostic Status Register (ISODIAGSTAT) (offset = C0h) ............................................. 285
6-1. PINMMR9 Control Register [Address Offset = 134h] ................................................................ 287
6-2. Output Multiplexing Example............................................................................................ 288
6-3. Input Multiplexing Example.............................................................................................. 296
6-4. ADC Trigger Event Signal Generation from ePWMx................................................................. 301
6-5. GIOA[5] and N2HET1_NDIS Input Multiplexing Scheme............................................................ 303
6-6. GIOB[2] and N2HET2_NDIS Input Multiplexing Scheme............................................................ 304
6-7. Synchronizing ePWMx Modules to N2HET1 Time-Base ............................................................ 305
6-8. nERROR and nERROR1 Input Multiplexing .......................................................................... 309
6-9. Using GIO Pin for External DMA Request............................................................................. 310
6-10. REVISION_REG: Revision Register (Offset = 00h).................................................................. 313
6-11. BOOT_REG: Boot Mode Register (Offset = 20h) .................................................................... 314
6-12. KICK_REG0: Kicker Register 0 (Offset = 38h) ....................................................................... 314
6-13. KICK_REG1: Kicker Register 1 (Offset = 3Ch)....................................................................... 314
6-14. ERR_RAW_STATUS_REG: Error Raw Status / Set Register (Offset = E0h) .................................... 315
6-15. ERR_ENABLED_STATUS_REG: Error Enabled Status / Clear Register (Offset = E4h)....................... 316
6-16. ERR_ENABLE_REG: Error Signaling Enable Register (Offset = E8h)............................................ 317
6-17. ERR_ENABLE_CLR_REG: Error Signaling Enable Clear Register (Offset = ECh) ............................. 318
6-18. FAULT_ADDRESS_REG: Fault Address Register (Offset = F4h) ................................................. 318
6-19. FAULT_STATUS_REG: Fault Status Register (Offset = F8h)...................................................... 319
6-20. FAULT_CLEAR_REG: Fault Clear Register (Offset = FCh) ........................................................ 320
6-21. PINMMRnn: Pin Multiplexing Control Registers (Offset = 110h-1A4h) ............................................ 320
6-22. PINMMRnn: Pin Multiplexing Control Registers (Offset = 250h-29Ch)............................................ 321
6-23. PINMMRnn: Pin Multiplexing Control Registers (Offset = 390h-3DCh) ........................................... 321
7-1. ECC Byte Mapping ....................................................................................................... 329
7-2. TI OTP Bank 0 Sector Information ..................................................................................... 330
7-3. TI OTP Bank 0 Package and Memory Size Information............................................................. 331
7-4. TI OTP Bank 0 LPO Trim and Max HCLK Information .............................................................. 331
7-5. TI OTP Bank 0 Symbolization Information (F008 01E0h-F008 01FFh) ........................................... 332
7-6. TI OTP Bank 0 Temperature Sensor 1 Calibration Information (F008 0310h-F008 031Fh).................... 332
7-7. TI OTP Bank 0 Temperature Sensor 2 Calibration Information (F008 0320h-F008 032Fh).................... 332
7-8. TI OTP Bank 0 Temperature Sensor 3 Calibration Information (F008 0330h-F008 033Fh).................... 332
7-9. TI OTP Bank 0 Deliberate ECC Error Information.................................................................... 333
7-10. Flash Read Control Register (FRDCNTL) (offset = 00h) ............................................................ 340
7-11. EEPROM Error correction control Register (EE_FEDACCTRL1) (offset = 08h) ................................. 341
7-12. Flash PortA Error and Status Register (FEDAC_PASTATUS) (offset = 14h) .................................... 342
7-13. Flash PortB Error and Status Register (FEDAC_PBSTATUS) (offset = 18h) .................................... 343
7-14. Flash Global Error and Status Register (FEDAC_GBLSTATUS) (offset = 1Ch) ................................. 344
7-15. Flash Error Detection and Correction Sector Disable Register (FEDACSDIS) (offset = 24h) .................. 345
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SPNU562–May 2014 List of Figures
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