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2-95. Peripheral Power-Down Clear Register 3 (PSPWRDWNCLR) (offset = ACh) ................................... 222
2-96. Debug Frame Powerdown Set Register (PDPWRDWNSET) (offset = C0h) ..................................... 222
2-97. Debug Frame Powerdown Clear Register (PDPWRDWNCLR) (offset = C4h)................................... 223
2-98. MasterID Protection Write Enable Register (MSTIDWRENA) (offset = 200h).................................... 223
2-99. MasterID Enable Register (MSTIDENA) (offset = 204h) ............................................................ 224
2-100. MasterID Diagnostic Control Register (MSTIDDIAGCTRL) (offset = 208h)....................................... 225
2-101. Peripheral Frame 0 MasterID Protection Register_L (PS0MSTID_L) (offset = 300h) ........................... 226
2-102. Peripheral Frame 0 MasterID Protection Register_H (PS0MSTID_H) (offset = 304h) .......................... 227
2-103. Peripheral Frame n MasterID Protection Register_L/H (PSnMSTID_L/H) (offset = 308h-3FCh) .............. 228
2-104. Privileged Peripheral Frame 0 MasterID Protection Register_L (PPS0MSTID_L) (offset = 400h)............. 229
2-105. Privileged Peripheral Frame 0 MasterID Protection Register_H (PPS0MSTID_H) (offset = 404h)............ 230
2-106. Privileged Peripheral Frame n MasterID Protection Register_L/H (PPSnMSTID_L/H) (offset = 408h-43Ch) 231
2-107. Privileged Peripheral Extended Frame 0 MasterID Protection Register_L (PPSE0MSTID_L) (offset =
440h) ....................................................................................................................... 232
2-108. Privileged Peripheral Extended Frame 0 MasterID Protection Register_H (PPSE0MSTID_H) (offset =
444h) ....................................................................................................................... 233
2-109. Privileged Peripheral Extended Frame n MasterID Protection Register_L/H (PPSEnMSTID_L/H) (offset =
448h-53Ch) ................................................................................................................ 234
2-110. Peripheral Memory Frame MasterID Protection Register (PCSnMSTID) (offset = 540h-5BCh) ............... 235
2-111. Privileged Peripheral Memory Frame MasterID Protection Register (PPCSnMSTID) (offset = 5C0h-5DCh) 236
3-1. System Level Block Diagram............................................................................................ 239
3-2. SCM Block Diagram...................................................................................................... 240
3-3. Timeout Threshold Compare............................................................................................ 241
3-4. SCM Control Block ....................................................................................................... 241
3-5. SCM REVID Register (SCMREVID) (offset = 00h)................................................................... 245
3-6. SCM Control Register (SCMCNTRL) (offset = 04h) ................................................................. 246
3-7. SCM Compare Threshold Counter Register (SCMTHRESHOLD) (offset = 08h) ................................ 247
3-8. SCM Initiator Error0 Status Register (SCMIAERR0STAT) (offset = 10h)......................................... 248
3-9. SCM Initiator Error1 Status Register (SCMIAERR1STAT) (offset = 14h)......................................... 248
3-10. SCM Initiator Active Status Register (SCMIASTAT) (offset = 18h) ................................................ 249
3-11. SCM Target Active Status Register (SCMTASTAT) (offset = 20h) ................................................ 249
4-1. Interconnect Block Diagram ............................................................................................. 251
4-2. SDC Status Register (SDC_STATUS) (offset = 00h)................................................................ 258
4-3. SDC Control Register (SDC_STATUS) (offset = 04h)............................................................... 259
4-4. Error Generic Parity Register (ERR_GENERIC_PARITY) (offset = 08h) ......................................... 259
4-5. Error Unexpected Transaction Register (ERR_UNEXPECTED_TRANS) (offset = 0Ch) ....................... 260
4-6. Error Transaction ID Register (ERR_TRANS_ID) (offset = 10h) ................................................... 260
4-7. Error Transaction Signature Register (ERR_TRANS_SIGNATURE) (offset = 14h) ............................. 261
4-8. Error Transaction Type Register (ERR_TRANS_TYPE) (offset = 18h) ........................................... 261
4-9. Error User Parity Register (ERR_USER_PARITY) (offset = 1Ch) ................................................. 262
4-10. Slave Error Unexpected Master ID Register (SERR_UNEXPECTED_MID) (offset = 20h)..................... 262
4-11. Slave Error Address Decode Register (SERR_ADDR_DECODE) (offset = 24h)................................ 263
4-12. Slave Error User Parity Register (SERR_USER_PARITY) (offset = 28h) ........................................ 263
5-1. PMM Block Diagram...................................................................................................... 266
5-2. Core Power Domains..................................................................................................... 267
5-3. Logic Power Domain Control Register (LOGICPDPWRCTRL0) (offset = 00h) .................................. 271
5-4. Logic Power Domain Control Register (LOGICPDPWRCTRL1) (offset = 04h) .................................. 272
5-5. Power Domain Clock Disable Register (PDCLKDISREG) (offset = 20h) ......................................... 273
5-6. Power Domain Clock Disable Set Register (PDCLKDISSETREG) (offset = 24h) ............................... 274
5-7. Power Domain Clock Disable Clear Register (PDCLKDISCLRREG) (offset = 28h)............................. 275
34
List of Figures SPNU562–May 2014
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