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35.3.13 DMM Destination x Blocksize 1 (DMMDESTxBL1) ..................................................... 1855
35.3.14 DMM Destination x Region 2 (DMMDESTxREG2)...................................................... 1856
35.3.15 DMM Destination x Blocksize 2 (DMMDESTxBL2) ..................................................... 1857
35.3.16 DMM Pin Control 0 (DMMPC0) ............................................................................ 1858
35.3.17 DMM Pin Control 1 (DMMPC1) ............................................................................ 1859
35.3.18 DMM Pin Control 2 (DMMPC2) ............................................................................ 1861
35.3.19 DMM Pin Control 3 (DMMPC3) ............................................................................ 1862
35.3.20 DMM Pin Control 4 (DMMPC4) ............................................................................ 1863
35.3.21 DMM Pin Control 5 (DMMPC5) ............................................................................ 1865
35.3.22 DMM Pin Control 6 (DMMPC6) ............................................................................ 1866
35.3.23 DMM Pin Control 7 (DMMPC7) ............................................................................ 1868
35.3.24 DMM Pin Control 8 (DMMPC8) ............................................................................ 1869
36 RAM Trace Port (RTP)...................................................................................................... 1871
36.1 Overview.................................................................................................................. 1872
36.1.1 Features ........................................................................................................ 1872
36.1.2 Block Diagram ................................................................................................. 1873
36.2 Module Operation ....................................................................................................... 1874
36.2.1 Trace Mode .................................................................................................... 1874
36.2.2 Direct Data Mode (DDM)..................................................................................... 1876
36.2.3 Trace Regions ................................................................................................. 1876
36.2.4 Overflow/Empty Handling .................................................................................... 1878
36.2.5 Signal Description............................................................................................. 1878
36.2.6 Data Rate ...................................................................................................... 1879
36.2.7 GIO Function................................................................................................... 1880
36.3 RTP Control Registers.................................................................................................. 1880
36.3.1 RTP Global Control Register (RTPGLBCTRL)............................................................ 1881
36.3.2 RTP Trace Enable Register (RTPTRENA) ................................................................ 1884
36.3.3 RTP Global Status Register (RTPGSR).................................................................... 1886
36.3.4 RTP RAM 1 Trace Region Registers (RTPRAM1REG[1:2]) ............................................ 1888
36.3.5 RTP RAM 2 Trace Region Registers (RTPRAM2REG[1:2]) ............................................ 1889
36.3.6 RTP RAM 3 Trace Region Registers (RTPRAM3REG[1:2]) ............................................ 1890
36.3.7 RTP Peripheral Trace Region Registers (RTPPERREG[1:2]) .......................................... 1892
36.3.8 RTP Direct Data Mode Write Register (RTPDDMW)..................................................... 1893
36.3.9 RTP Pin Control 0 Register (RTPPC0)..................................................................... 1894
36.3.10 RTP Pin Control 1 Register (RTPPC1) ................................................................... 1895
36.3.11 RTP Pin Control 2 Register (RTPPC2) ................................................................... 1896
36.3.12 RTP Pin Control 3 Register (RTPPC3) ................................................................... 1897
36.3.13 RTP Pin Control 4 Register (RTPPC4) ................................................................... 1898
36.3.14 RTP Pin Control 5 Register (RTPPC5) ................................................................... 1899
36.3.15 RTP Pin Control 6 Register (RTPPC6) ................................................................... 1900
36.3.16 RTP Pin Control 7 Register (RTPPC7) ................................................................... 1902
36.3.17 RTP Pin Control 8 Register (RTPPC8) ................................................................... 1903
37 eFuse Controller ............................................................................................................. 1904
37.1 Overview.................................................................................................................. 1905
37.2 Introduction............................................................................................................... 1905
37.3 eFuse Controller Testing ............................................................................................... 1905
37.3.1 eFuse Controller Connections to ESM ..................................................................... 1905
37.3.2 Checking for eFuse Errors After Power Up................................................................ 1905
37.4 eFuse Controller Registers............................................................................................. 1908
37.4.1 EFC Boundary Control Register (EFCBOUND)........................................................... 1908
37.4.2 EFC Pins Register (EFCPINS) .............................................................................. 1910
37.4.3 EFC Error Status Register (EFCERRSTAT)............................................................... 1911
37.4.4 EFC Self Test Cycles Register (EFCSTCY)............................................................... 1911
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Contents SPNU562–May 2014
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