Datasheet
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34.1 Introduction............................................................................................................... 1713
34.1.1 Submodule Overview ......................................................................................... 1713
34.1.2 Register Mapping ............................................................................................. 1716
34.2 ePWM Submodules..................................................................................................... 1717
34.2.1 Overview ....................................................................................................... 1717
34.2.2 Time-Base (TB) Submodule ................................................................................. 1719
34.2.3 Counter-Compare (CC) Submodule ........................................................................ 1727
34.2.4 Action-Qualifier (AQ) Submodule ........................................................................... 1732
34.2.5 Dead-Band Generator (DB) Submodule ................................................................... 1745
34.2.6 PWM-Chopper (PC) Submodule ............................................................................ 1750
34.2.7 Trip-Zone (TZ) Submodule................................................................................... 1754
34.2.8 Event-Trigger (ET) Submodule.............................................................................. 1760
34.2.9 Digital Compare (DC) Submodule .......................................................................... 1765
34.2.10 Proper Interrupt Initialization Procedure .................................................................. 1771
34.3 Application Examples................................................................................................... 1772
34.3.1 Overview of Multiple Modules .............................................................................. 1772
34.3.2 Key Configuration Capabilities .............................................................................. 1772
34.3.3 Controlling Multiple Buck Converters With Independent Frequencies ................................. 1774
34.3.4 Controlling Multiple Buck Converters With Same Frequencies ......................................... 1777
34.3.5 Controlling Multiple Half H-Bridge (HHB) Converters .................................................... 1780
34.3.6 Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM) ....................................... 1782
34.3.7 Practical Applications Using Phase Control Between PWM Modules.................................. 1785
34.4 ePWM Registers ........................................................................................................ 1787
34.4.1 Time-Base Submodule Registers ........................................................................... 1788
34.4.2 Counter-Compare Submodule Registers .................................................................. 1792
34.4.3 Action-Qualifier Submodule Registers...................................................................... 1795
34.4.4 Dead-Band Submodule Registers .......................................................................... 1799
34.4.5 Trip-Zone Submodule Registers ............................................................................ 1802
34.4.6 Event-Trigger Submodule Registers........................................................................ 1810
34.4.7 PWM-Chopper Submodule Register........................................................................ 1816
34.4.8 Digital Compare Submodule Registers..................................................................... 1818
35 Data Modification Module (DMM)....................................................................................... 1825
35.1 Overview.................................................................................................................. 1826
35.1.1 Features ........................................................................................................ 1826
35.1.2 Block Diagram ................................................................................................. 1826
35.2 Module Operation ....................................................................................................... 1827
35.2.1 Data Format.................................................................................................... 1827
35.2.2 Data Port ....................................................................................................... 1829
35.2.3 Error Handling ................................................................................................. 1830
35.2.4 Interrupts ....................................................................................................... 1831
35.3 Control Registers........................................................................................................ 1832
35.3.1 DMM Global Control Register (DMMGLBCTRL).......................................................... 1833
35.3.2 DMM Interrupt Set Register (DMMINTSET) ............................................................... 1835
35.3.3 DMM Interrupt Clear Register (DMMINTCLR) ............................................................ 1839
35.3.4 DMM Interrupt Level Register (DMMINTLVL) ............................................................. 1844
35.3.5 DMM Interrupt Flag Register (DMMINTFLG).............................................................. 1846
35.3.6 DMM Interrupt Offset 1 Register (DMMOFF1) ............................................................ 1850
35.3.7 DMM Interrupt Offset 2 Register (DMMOFF2) ............................................................ 1851
35.3.8 DMM Direct Data Mode Destination Register (DMMDDMDEST)....................................... 1852
35.3.9 DMM Direct Data Mode Blocksize Register (DMMDDMBL)............................................. 1852
35.3.10 DMM Direct Data Mode Pointer Register (DMMDDMPT) .............................................. 1853
35.3.11 DMM Direct Data Mode Interrupt Pointer Register (DMMINTPT) ..................................... 1853
35.3.12 DMM Destination x Region 1 (DMMDESTxREG1)...................................................... 1854
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SPNU562–May 2014 Contents
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