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31.5.6 Receive Teardown Register (RXTEARDOWN) ........................................................... 1602
31.5.7 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) ................................... 1603
31.5.8 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) ................................. 1604
31.5.9 Transmit Interrupt Mask Set Register (TXINTMASKSET) ............................................... 1605
31.5.10 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) ....................................... 1606
31.5.11 MAC Input Vector Register (MACINVECTOR) .......................................................... 1607
31.5.12 MAC End Of Interrupt Vector Register (MACEOIVECTOR) ........................................... 1608
31.5.13 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW).................................. 1609
31.5.14 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) ................................ 1610
31.5.15 Receive Interrupt Mask Set Register (RXINTMASKSET) .............................................. 1611
31.5.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)........................................ 1612
31.5.17 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) ................................... 1613
31.5.18 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED).................................. 1613
31.5.19 MAC Interrupt Mask Set Register (MACINTMASKSET)................................................ 1614
31.5.20 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) ......................................... 1614
31.5.21 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) ......... 1615
31.5.22 Receive Unicast Enable Set Register (RXUNICASTSET) ............................................. 1617
31.5.23 Receive Unicast Clear Register (RXUNICASTCLEAR) ................................................ 1618
31.5.24 Receive Maximum Length Register (RXMAXLEN)...................................................... 1618
31.5.25 Receive Buffer Offset Register (RXBUFFEROFFSET)................................................. 1619
31.5.26 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)................. 1619
31.5.27 Receive Channel Flow Control Threshold Registers (RX0FLOWTHRESH-RX7FLOWTHRESH) 1620
31.5.28 Receive Channel Free Buffer Count Registers (RX0FREEBUFFER-RX7FREEBUFFER) ........ 1620
31.5.29 MAC Control Register (MACCONTROL) ................................................................. 1621
31.5.30 MAC Status Register (MACSTATUS)..................................................................... 1623
31.5.31 Emulation Control Register (EMCONTROL) ............................................................. 1625
31.5.32 FIFO Control Register (FIFOCONTROL)................................................................. 1625
31.5.33 MAC Configuration Register (MACCONFIG) ............................................................ 1626
31.5.34 Soft Reset Register (SOFTRESET) ....................................................................... 1626
31.5.35 MAC Source Address Low Bytes Register (MACSRCADDRLO) ..................................... 1627
31.5.36 MAC Source Address High Bytes Register (MACSRCADDRHI)...................................... 1627
31.5.37 MAC Hash Address Register 1 (MACHASH1)........................................................... 1628
31.5.38 MAC Hash Address Register 2 (MACHASH2)........................................................... 1628
31.5.39 Back Off Test Register (BOFFTEST) ..................................................................... 1629
31.5.40 Transmit Pacing Algorithm Test Register (TPACETEST) .............................................. 1629
31.5.41 Receive Pause Timer Register (RXPAUSE) ............................................................. 1630
31.5.42 Transmit Pause Timer Register (TXPAUSE) ............................................................ 1630
31.5.43 MAC Address Low Bytes Register (MACADDRLO) .................................................... 1631
31.5.44 MAC Address High Bytes Register (MACADDRHI)..................................................... 1632
31.5.45 MAC Index Register (MACINDEX) ........................................................................ 1632
31.5.46 Transmit Channel DMA Head Descriptor Pointer Registers (TX0HDP-TX7HDP) .................. 1633
31.5.47 Receive Channel DMA Head Descriptor Pointer Registers (RX0HDP-RX7HDP) .................. 1633
31.5.48 Transmit Channel Completion Pointer Registers (TX0CP-TX7CP) ................................... 1634
31.5.49 Receive Channel Completion Pointer Registers (RX0CP-RX7CP) ................................... 1634
31.5.50 Network Statistics Registers ............................................................................... 1635
32 Enhanced Capture (eCAP) Module .................................................................................... 1644
32.1 Introduction............................................................................................................... 1645
32.1.1 Features ........................................................................................................ 1645
32.1.2 Description ..................................................................................................... 1645
32.2 Basic Operation.......................................................................................................... 1646
32.2.1 Capture and APWM Operating Mode ...................................................................... 1646
32.2.2 Capture Mode Description ................................................................................... 1647
32.3 Application of the ECAP Module ..................................................................................... 1653
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SPNU562–May 2014 Contents
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