Datasheet

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31.2.2 Memory Map................................................................................................... 1527
31.2.3 Signal Descriptions............................................................................................ 1528
31.2.4 MII / RMII Signal Multiplexing Control ...................................................................... 1531
31.2.5 Ethernet Protocol Overview.................................................................................. 1532
31.2.6 Programming Interface ....................................................................................... 1533
31.2.7 EMAC Control Module........................................................................................ 1544
31.2.8 MDIO Module .................................................................................................. 1545
31.2.9 EMAC Module ................................................................................................. 1550
31.2.10 MAC Interface................................................................................................ 1552
31.2.11 Packet Receive Operation.................................................................................. 1556
31.2.12 Packet Transmit Operation ................................................................................. 1561
31.2.13 Receive and Transmit Latency............................................................................. 1562
31.2.14 Transfer Node Priority....................................................................................... 1562
31.2.15 Reset Considerations ....................................................................................... 1563
31.2.16 Initialization ................................................................................................... 1564
31.2.17 Interrupt Support............................................................................................. 1566
31.2.18 Power Management ......................................................................................... 1570
31.2.19 Emulation Considerations .................................................................................. 1570
31.3 EMAC Control Module Registers...................................................................................... 1571
31.3.1 EMAC Control Module Revision ID Register (REVID) ................................................... 1572
31.3.2 EMAC Control Module Software Reset Register (SOFTRESET)....................................... 1572
31.3.3 EMAC Control Module Interrupt Control Register (INTCONTROL) .................................... 1573
31.3.4 EMAC Control Module Receive Threshold Interrupt Enable Registers (C0RXTHRESHEN) ....... 1574
31.3.5 EMAC Control Module Receive Interrupt Enable Registers (C0RXEN) ............................... 1575
31.3.6 EMAC Control Module Transmit Interrupt Enable Registers (C0TXEN) ............................... 1576
31.3.7 EMAC Control Module Miscellaneous Interrupt Enable Registers (C0MISCEN) ..................... 1577
31.3.8 EMAC Control Module Receive Threshold Interrupt Status Registers (C0RXTHRESHSTAT) ..... 1578
31.3.9 EMAC Control Module Receive Interrupt Status Registers (C0RXSTAT) ............................. 1579
31.3.10 EMAC Control Module Transmit Interrupt Status Registers (C0TXSTAT) ........................... 1580
31.3.11 EMAC Control Module Miscellaneous Interrupt Status Registers (C0MISCSTAT) ................. 1581
31.3.12 EMAC Control Module Receive Interrupts Per Millisecond Registers (C0RXIMAX)................ 1582
31.3.13 EMAC Control Module Transmit Interrupts Per Millisecond Registers (C0TXIMAX) ............... 1583
31.4 MDIO Registers.......................................................................................................... 1584
31.4.1 MDIO Revision ID Register (REVID) ....................................................................... 1584
31.4.2 MDIO Control Register (CONTROL) ....................................................................... 1585
31.4.3 PHY Acknowledge Status Register (ALIVE)............................................................... 1586
31.4.4 PHY Link Status Register (LINK) ........................................................................... 1586
31.4.5 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW)........................... 1587
31.4.6 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) ......................... 1588
31.4.7 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW).................. 1589
31.4.8 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) ................ 1590
31.4.9 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) .............. 1591
31.4.10 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR)....... 1592
31.4.11 MDIO User Access Register 0 (USERACCESS0) ...................................................... 1593
31.4.12 MDIO User PHY Select Register 0 (USERPHYSEL0).................................................. 1594
31.4.13 MDIO User Access Register 1 (USERACCESS1) ...................................................... 1595
31.4.14 MDIO User PHY Select Register 1 (USERPHYSEL1).................................................. 1596
31.5 EMAC Module Registers ............................................................................................... 1597
31.5.1 Transmit Revision ID Register (TXREVID) ................................................................ 1600
31.5.2 Transmit Control Register (TXCONTROL)................................................................. 1600
31.5.3 Transmit Teardown Register (TXTEARDOWN)........................................................... 1601
31.5.4 Receive Revision ID Register (RXREVID)................................................................. 1601
31.5.5 Receive Control Register (RXCONTROL) ................................................................. 1602
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Contents SPNU562–May 2014
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