Datasheet

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30.3.3 Slave Transmitter Mode...................................................................................... 1495
30.3.4 Slave Receiver Mode ........................................................................................ 1495
30.3.5 Low Power Mode.............................................................................................. 1496
30.3.6 Free Run Mode................................................................................................ 1496
30.3.7 Ignore NACK Mode .......................................................................................... 1496
30.4 I2C Module Integrity..................................................................................................... 1497
30.4.1 Arbitration ...................................................................................................... 1497
30.4.2 I2C Clock Generation and Synchronization ............................................................... 1498
30.4.3 Prescaler ....................................................................................................... 1498
30.4.4 Noise Filter ..................................................................................................... 1498
30.5 Operational Information................................................................................................. 1499
30.5.1 I2C Module Interrupts......................................................................................... 1499
30.5.2 DMA Controller Events ....................................................................................... 1500
30.5.3 I2C Enable/Disable............................................................................................ 1500
30.5.4 General Purpose I/O.......................................................................................... 1500
30.5.5 Pull Up/Pull Down Function.................................................................................. 1501
30.5.6 Open Drain Function.......................................................................................... 1501
30.6 I2C Control Registers................................................................................................... 1502
30.6.1 I2C Own Address Manager (I2COAR) ..................................................................... 1503
30.6.2 I2C Interrupt Mask Register (I2CIMR)...................................................................... 1504
30.6.3 I2C Status Register (I2CSTR) ............................................................................... 1505
30.6.4 I2C Clock Divider Low Register (I2CCKL) ................................................................. 1508
30.6.5 I2C Clock Control High Register (I2CCKH)................................................................ 1508
30.6.6 I2C Data Count Register (I2CCNT)......................................................................... 1509
30.6.7 I2C Data Receive Register (I2CDRR) ...................................................................... 1509
30.6.8 I2C Slave Address Register (I2CSAR) ..................................................................... 1510
30.6.9 I2C Data Transmit Register (I2CDXR) ..................................................................... 1510
30.6.10 I2C Mode Register (I2CMDR).............................................................................. 1511
30.6.11 I2C Interrupt Vector Register (I2CIVR) ................................................................... 1514
30.6.12 I2C Extended Mode Register (I2CEMDR)................................................................ 1515
30.6.13 I2C Prescale Register (I2CPSC) .......................................................................... 1515
30.6.14 I2C Peripheral ID Register 1 (I2CPID1) .................................................................. 1516
30.6.15 I2C Peripheral ID Register 2 (I2CPID2) .................................................................. 1516
30.6.16 I2C DMA Control Register (I2CDMACR) ................................................................. 1517
30.6.17 I2C Pin Function Register (I2CPFNC) .................................................................... 1517
30.6.18 I2C Pin Direction Register (I2CPDIR)..................................................................... 1518
30.6.19 I2C Data Input Register (I2CDIN) ......................................................................... 1518
30.6.20 I2C Data Output Register (I2CDOUT) .................................................................... 1519
30.6.21 I2C Data Set Register (I2CDSET)......................................................................... 1519
30.6.22 I2C Data Clear Register (I2CDCLR) ...................................................................... 1520
30.6.23 I2C Pin Open Drain Register (I2CPDR) .................................................................. 1520
30.6.24 I2C Pull Disable Register (I2CPDIS) ...................................................................... 1521
30.6.25 I2C Pull Select Register (I2CPSEL)....................................................................... 1521
30.6.26 I2C Pins Slew Rate Select Register (I2CSRS) .......................................................... 1522
30.7 Sample Waveforms ..................................................................................................... 1523
31 EMAC/MDIO Module ........................................................................................................ 1524
31.1 Introduction............................................................................................................... 1525
31.1.1 Purpose of the Peripheral .................................................................................... 1525
31.1.2 Features ........................................................................................................ 1525
31.1.3 Functional Block Diagram.................................................................................... 1526
31.1.4 Industry Standard(s) Compliance Statement .............................................................. 1527
31.2 Architecture .............................................................................................................. 1527
31.2.1 Clock Control .................................................................................................. 1527
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SPNU562–May 2014 Contents
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