Datasheet

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29.3.4 Error Interrupts ................................................................................................ 1448
29.4 SCI DMA Interface ...................................................................................................... 1449
29.4.1 Receive DMA Requests...................................................................................... 1449
29.4.2 Transmit DMA Requests ..................................................................................... 1449
29.5 SCI Configurations ...................................................................................................... 1451
29.5.1 Receiving Data ................................................................................................ 1451
29.5.2 Transmitting Data ............................................................................................. 1452
29.6 SCI Low Power Mode .................................................................................................. 1452
29.6.1 Sleep Mode for Multiprocessor Communication .......................................................... 1453
29.7 SCI Control Registers .................................................................................................. 1454
29.7.1 SCI Global Control Register 0 (SCIGCR0) ................................................................ 1455
29.7.2 SCI Global Control Register 1 (SCIGCR1) ................................................................ 1456
29.7.3 SCI Set Interrupt Register (SCISETINT) .................................................................. 1459
29.7.4 SCI Clear Interrupt Register (SCICLEARINT) ............................................................ 1461
29.7.5 SCI Set Interrupt Level Register (SCISETINTLVL) ...................................................... 1463
29.7.6 SCI Clear Interrupt Level Register (SCICLEARINTLVL) ................................................ 1464
29.7.7 SCI Flags Register (SCIFLR) ............................................................................... 1466
29.7.8 SCI Interrupt Vector Offset 0 (SCIINTVECT0) ........................................................... 1470
29.7.9 SCI Interrupt Vector Offset 1 (SCIINTVECT1) ........................................................... 1470
29.7.10 SCI Format Control Register (SCIFORMAT) ............................................................ 1471
29.7.11 Baud Rate Selection Register (BRS) ..................................................................... 1472
29.7.12 SCI Data Buffers (SCIED, SCIRD, SCITD) .............................................................. 1473
29.7.13 SCI Pin I/O Control Register 0 (SCIPIO0) ............................................................... 1474
29.7.14 SCI Pin I/O Control Register 1 (SCIPIO1) ............................................................... 1475
29.7.15 SCI Pin I/O Control Register 2 (SCIPIO2) ............................................................... 1476
29.7.16 SCI Pin I/O Control Register 3 (SCIPIO3) ............................................................... 1477
29.7.17 SCI Pin I/O Control Register 4 (SCIPIO4) ............................................................... 1478
29.7.18 SCI Pin I/O Control Register 5 (SCIPIO5) ............................................................... 1479
29.7.19 SCI Pin I/O Control Register 6 (SCIPIO6) ............................................................... 1480
29.7.20 SCI Pin I/O Control Register 7 (SCIPIO7) ............................................................... 1481
29.7.21 SCI Pin I/O Control Register 8 (SCIPIO8) ............................................................... 1481
29.7.22 Input/Output Error Enable (IODFTCTRL) Register ..................................................... 1482
29.8 GPIO Functionality ...................................................................................................... 1484
29.8.1 GPIO Functionality ............................................................................................ 1484
29.8.2 Under Reset ................................................................................................... 1484
29.8.3 Out of Reset ................................................................................................... 1485
29.8.4 Open-Drain Feature Enabled on a Pin ..................................................................... 1485
29.8.5 Summary ....................................................................................................... 1485
30 Inter-Integrated Circuit (I2C) Module.................................................................................. 1486
30.1 Overview.................................................................................................................. 1487
30.1.1 Introduction to the I2C Module .............................................................................. 1487
30.1.2 Functional Overview .......................................................................................... 1488
30.1.3 Clock Generation.............................................................................................. 1490
30.2 I2C Module Operation .................................................................................................. 1491
30.2.1 Input and Output Voltage Levels ............................................................................ 1491
30.2.2 I2C Module Reset Conditions ............................................................................... 1491
30.2.3 I2C Module Data Validity .................................................................................... 1491
30.2.4 I2C Module Start and Stop Conditions ..................................................................... 1492
30.2.5 Serial Data Formats........................................................................................... 1492
30.2.6 NACK Bit Generation ......................................................................................... 1494
30.3 I2C Operation Modes ................................................................................................... 1495
30.3.1 Master Transmitter Mode .................................................................................... 1495
30.3.2 Master Receiver Mode ....................................................................................... 1495
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Contents SPNU562–May 2014
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