Datasheet
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27.3.28 Transfer Group Interrupt Level Set Register (TGITLVST).............................................. 1300
27.3.29 Transfer Group Interrupt Level Clear Register (TGITLVCR)........................................... 1301
27.3.30 Transfer Group Interrupt Flag Register (TGINTFLAG) ................................................. 1302
27.3.31 Tick Count Register (TICKCNT) ........................................................................... 1303
27.3.32 Last TG End Pointer (LTGPEND) ......................................................................... 1304
27.3.33 TGx Control Registers (TGxCTRL)........................................................................ 1305
27.3.34 DMA Channel Control Register (DMAxCTRL) ........................................................... 1308
27.3.35 DMAxCOUNT Register (ICOUNT) ........................................................................ 1310
27.3.36 DMA Large Count (DMACNTLEN) ........................................................................ 1311
27.3.37 Parity/ECC Control Register (PAR_ECC_CTRL)........................................................ 1312
27.3.38 Parity/ECC Status Register (PAR_ECC_STAT)......................................................... 1313
27.3.39 Uncorrectable Parity or Double Bit ECC Error Address Register - RXRAM (UERRADDR1)...... 1314
27.3.40 Uncorrectable Parity or Double Bit ECC Error Address Register - TXRAM (UERRADDR0) ...... 1316
27.3.41 RXRAM Overrun Buffer Address Register (RXOVRN_BUF_ADDR) ................................. 1317
27.3.42 I/O-Loopback Test Control Register (IOLPBKTSTCR) ................................................. 1318
27.3.43 SPI Extended Prescale Register 1 (EXTENDED_PRESCALE1 for SPIFMT0 and SPIFMT1).... 1320
27.3.44 SPI Extended Prescale Register 2 (EXTENDED_PRESCALE2 for SPIFMT2 and SPIFMT3).... 1322
27.3.45 ECC Diagnostic Control Register (ECCDIAG_CTRL) .................................................. 1323
27.3.46 ECC Diagnostic Status Register (ECCDIAG_STAT) ................................................... 1324
27.3.47 Single Bit Error Address Register - RXRAM (SBERRADDR1) ........................................ 1325
27.3.48 Single Bit Error Address Register - TXRAM (SBERRADDR0) ........................................ 1326
27.4 Multi-buffer RAM ........................................................................................................ 1327
27.4.1 Multi-buffer RAM Auto Initialization ......................................................................... 1328
27.4.2 Multi-buffer RAM Register Summary ....................................................................... 1328
27.4.3 Multi-buffer RAM Transmit Data Register.................................................................. 1329
27.4.4 Multi-buffer RAM Receive Buffer Register ................................................................. 1331
27.5 Parity\ECC Memory..................................................................................................... 1333
27.5.1 Example of Parity Memory Organization................................................................... 1336
27.5.2 Example of ECC Memory Organization .................................................................... 1337
27.6 MibSPI Pin Timing Parameters........................................................................................ 1338
27.6.1 Master Mode Timings for SPI/MibSPI ...................................................................... 1338
27.6.2 Slave Mode Timings for SPI/MibSPI........................................................................ 1340
27.6.3 Master Mode Timing Parameter Details.................................................................... 1341
27.6.4 Slave Mode Timing Parameter Details ..................................................................... 1341
28 Serial Communication Interface (SCI)/Local Interconnect Network (LIN) Module..................... 1342
28.1 Introduction and Features.............................................................................................. 1343
28.1.1 SCI Features................................................................................................... 1343
28.1.2 LIN Features ................................................................................................... 1344
28.1.3 Block Diagram ................................................................................................. 1345
28.2 SCI ........................................................................................................................ 1348
28.2.1 SCI Communication Formats................................................................................ 1348
28.2.2 SCI Interrupts .................................................................................................. 1356
28.2.3 SCI DMA Interface ............................................................................................ 1359
28.2.4 SCI Configurations ............................................................................................ 1360
28.2.5 SCI Low Power Mode ........................................................................................ 1362
28.3 LIN......................................................................................................................... 1363
28.3.1 LIN Communication Formats ................................................................................ 1363
28.3.2 LIN Interrupts .................................................................................................. 1380
28.3.3 LIN DMA Interface ............................................................................................ 1380
28.3.4 LIN Configurations ............................................................................................ 1381
28.4 Low-Power Mode........................................................................................................ 1383
28.4.1 Entering Sleep Mode ......................................................................................... 1383
28.4.2 Wakeup......................................................................................................... 1384
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Contents SPNU562–May 2014
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