Datasheet

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26.17.27 IF3 Observation Register (DCAN IF3OBS) ............................................................. 1213
26.17.28 IF3 Mask Register (DCAN IF3MSK)..................................................................... 1215
26.17.29 IF3 Arbitration Register (DCAN IF3ARB) ............................................................... 1216
26.17.30 IF3 Message Control Register (DCAN IF3MCTL) ..................................................... 1217
26.17.31 IF3 Data A and Data B Registers (DCAN IF3DATA/DATB) .......................................... 1218
26.17.32 IF3 Update Enable Registers (DCAN IF3UPD12 to DCAN IF3UPD78) ............................ 1219
26.17.33 CAN TX IO Control Register (DCAN TIOC) ............................................................ 1220
26.17.34 CAN RX IO Control Register (DCAN RIOC)............................................................ 1221
27 Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin Option (MibSPIP) . 1223
27.1 Overview.................................................................................................................. 1224
27.1.1 Features ........................................................................................................ 1224
27.1.2 Pin Configurations............................................................................................. 1225
27.1.3 MibSPI /SPI Configurations.................................................................................. 1226
27.2 Basic Operation.......................................................................................................... 1226
27.2.1 SPI Mode....................................................................................................... 1226
27.2.2 MibSPI Mode .................................................................................................. 1228
27.2.3 DMA Requests ................................................................................................ 1229
27.2.4 Interrupts ....................................................................................................... 1231
27.2.5 Physical Interface ............................................................................................. 1233
27.2.6 Advanced Module Configuration Options .................................................................. 1237
27.2.7 General-Purpose I/O.......................................................................................... 1255
27.2.8 Low-Power Mode.............................................................................................. 1255
27.2.9 Safety Features................................................................................................ 1255
27.2.10 Test Features ................................................................................................ 1257
27.2.11 Module Configuration ....................................................................................... 1259
27.3 Control Registers........................................................................................................ 1261
27.3.1 SPI Global Control Register 0 (SPIGCR0)................................................................. 1262
27.3.2 SPI Global Control Register 1 (SPIGCR1)................................................................. 1263
27.3.3 SPI Interrupt Register (SPIINT0)............................................................................ 1264
27.3.4 SPI Interrupt Level Register (SPILVL)...................................................................... 1266
27.3.5 SPI Flag Register (SPIFLG) ................................................................................. 1267
27.3.6 SPI Pin Control Register 0 (SPIPC0)....................................................................... 1270
27.3.7 SPI Pin Control Register 1 (SPIPC1)....................................................................... 1271
27.3.8 SPI Pin Control Register 2 (SPIPC2)....................................................................... 1273
27.3.9 SPI Pin Control Register 3 (SPIPC3)....................................................................... 1274
27.3.10 SPI Pin Control Register 4 (SPIPC4) ..................................................................... 1275
27.3.11 SPI Pin Control Register 5 (SPIPC5) ..................................................................... 1277
27.3.12 SPI Pin Control Register 6 (SPIPC6) ..................................................................... 1278
27.3.13 SPI Pin Control Register 7 (SPIPC7) ..................................................................... 1280
27.3.14 SPI Pin Control Register 8 (SPIPC8) ..................................................................... 1281
27.3.15 SPI Transmit Data Register 0 (SPIDAT0) ................................................................ 1282
27.3.16 SPI Transmit Data Register 1 (SPIDAT1) ................................................................ 1283
27.3.17 SPI Receive Buffer Register (SPIBUF) ................................................................... 1284
27.3.18 SPI Emulation Register (SPIEMU) ........................................................................ 1286
27.3.19 SPI Delay Register (SPIDELAY) .......................................................................... 1286
27.3.20 SPI Default Chip Select Register (SPIDEF).............................................................. 1289
27.3.21 SPI Data Format Registers (SPIFMT[3:0]) ............................................................... 1290
27.3.22 Interrupt Vector 0 (INTVECT0)............................................................................. 1292
27.3.23 Interrupt Vector 1 (INTVECT1)............................................................................. 1293
27.3.24 Parallel/Modulo Mode Control Register (SPIPMCTRL)................................................. 1294
27.3.25 Multi-buffer Mode Enable Register (MIBSPIE)........................................................... 1297
27.3.26 TG Interrupt Enable Set Register (TGITENST).......................................................... 1298
27.3.27 TG Interrupt Enable Clear Register (TGITENCR)....................................................... 1299
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SPNU562–May 2014 Contents
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