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24.4.12 Interrupt Offset Register 0 (HTU INTOFF0).............................................................. 1092
24.4.13 Interrupt Offset Register 1 (HTU INTOFF1).............................................................. 1093
24.4.14 Buffer Initialization Mode Register (HTU BIM) ........................................................... 1094
24.4.15 Request Lost Flag Register (HTU RLOSTFL) ........................................................... 1096
24.4.16 Buffer Full Interrupt Flag Register (HTU BFINTFL) ..................................................... 1096
24.4.17 BER Interrupt Flag Register (HTU BERINTFL).......................................................... 1097
24.4.18 Memory Protection 1 Start Address Register (HTU MP1S)............................................ 1098
24.4.19 Memory Protection 1 End Address Register (HTU MP1E)............................................. 1098
24.4.20 Debug Control Register (HTU DCTRL) ................................................................... 1099
24.4.21 Watch Point Register (HTU WPR) ........................................................................ 1100
24.4.22 Watch Mask Register (HTU WMR)........................................................................ 1100
24.4.23 Module Identification Register (HTU ID).................................................................. 1101
24.4.24 Parity Control Register (HTU PCR) ....................................................................... 1102
24.4.25 Parity Address Register (HTU PAR) ...................................................................... 1103
24.4.26 Memory Protection Control and Status Register (HTU MPCS)........................................ 1104
24.4.27 Memory Protection Start Address Register 0 (HTU MP0S)............................................ 1107
24.4.28 Memory Protection End Address Register (HTU MP0E) ............................................... 1107
24.5 Double Control Packet Configuration Memory ...................................................................... 1108
24.5.1 Initial Full Address A Register (HTU IFADDRA) .......................................................... 1109
24.5.2 Initial Full Address B Register (HTU IFADDRB) .......................................................... 1109
24.5.3 Initial NHET Address and Control Register (HTU IHADDRCT) ......................................... 1110
24.5.4 Initial Transfer Count Register (HTU ITCOUNT).......................................................... 1111
24.5.5 Current Full Address A Register (HTU CFADDRA) ...................................................... 1112
24.5.6 Current Full Address B Register (HTU CFADDRB) ...................................................... 1113
24.5.7 Current Frame Count Register (HTU CFCOUNT) ........................................................ 1114
24.6 Examples ................................................................................................................. 1115
24.6.1 Application Examples for Setting the Transfer Modes of CP A and B of a DCP ..................... 1115
24.6.2 Software Example Sequence Assuming Circular Mode for Both CP A and B ........................ 1115
24.6.3 Example of an Interrupt Dispatch Flow for a Request Lost Interrupt................................... 1116
25 General-Purpose Input/Output (GIO) Module ...................................................................... 1117
25.1 Overview.................................................................................................................. 1118
25.2 Quick Start Guide ....................................................................................................... 1119
25.3 Functional Description of GIO Module................................................................................ 1121
25.3.1 I/O Functions................................................................................................... 1121
25.3.2 Interrupt Function ............................................................................................. 1121
25.3.3 GIO Block Diagram ........................................................................................... 1122
25.4 Device Modes of Operation............................................................................................ 1123
25.4.1 Emulation Mode ............................................................................................... 1123
25.4.2 Power-Down Mode (Low-Power Mode) .................................................................... 1123
25.5 GIO Control Registers .................................................................................................. 1124
25.5.1 GIO Global Control Register (GIOGCR0).................................................................. 1125
25.5.2 GIO Interrupt Detect Register (GIOINTDET) .............................................................. 1126
25.5.3 GIO Interrupt Polarity Register (GIOPOL) ................................................................. 1127
25.5.4 GIO Interrupt Enable Registers (GIOENASET and GIOENACLR) ..................................... 1128
25.5.5 GIO Interrupt Priority Registers (GIOLVLSET and GIOLVLCLR)....................................... 1130
25.5.6 GIO Interrupt Flag Register (GIOFLG) ..................................................................... 1133
25.5.7 GIO Offset Register 1 (GIOOFF1) .......................................................................... 1134
25.5.8 GIO Offset B Register (GIOOFF2).......................................................................... 1135
25.5.9 GIO Emulation A Register (GIOEMU1) .................................................................... 1136
25.5.10 GIO Emulation B Register (GIOEMU2) ................................................................... 1137
25.5.11 GIO Data Direction Registers (GIODIR[A-B])............................................................ 1138
25.5.12 GIO Data Input Registers (GIODIN[A-B])................................................................. 1138
25.5.13 GIO Data Output Registers (GIODOUT[A-B]) ........................................................... 1139
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Contents SPNU562–May 2014
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