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22.3.52 ADC Group1 Sample Cap Discharge Control Register (ADG1SAMPDISEN) ........................ 912
22.3.53 ADC Group2 Sample Cap Discharge Control Register (ADG2SAMPDISEN) ........................ 913
22.3.54 ADC Magnitude Compare Interrupt Control Registers (ADMAGINTxCR) ............................. 914
22.3.55 ADC Magnitude Compare Interruptx Mask Register (ADMAGINTxMASK)............................ 916
22.3.56 ADC Magnitude Compare Interrupt Enable Set Register (ADMAGINTENASET) .................... 917
22.3.57 ADC Magnitude Compare Interrupt Enable Clear Register (ADMAGINTENACLR).................. 917
22.3.58 ADC Magnitude Compare Interrupt Flag Register (ADMAGINTFLG).................................. 918
22.3.59 ADC Magnitude Compare Interrupt Offset Register (ADMAGINTOFF)................................ 918
22.3.60 ADC Event Group FIFO Reset Control Register (ADEVFIFORESETCR)............................. 919
22.3.61 ADC Group1 FIFO Reset Control Register (ADG1FIFORESETCR) ................................... 919
22.3.62 ADC Group2 FIFO Reset Control Register (ADG2FIFORESETCR) ................................... 920
22.3.63 ADC Event Group RAM Write Address Register (ADEVRAMWRADDR) ............................. 920
22.3.64 ADC Group1 RAM Write Address Register (ADG1RAMWRADDR).................................... 921
22.3.65 ADC Group2 RAM Write Address Register (ADG2RAMWRADDR).................................... 921
22.3.66 ADC Parity Control Register (ADPARCR) ................................................................. 922
22.3.67 ADC Parity Error Address Register (ADPARADDR) ..................................................... 923
22.3.68 ADC Power-Up Delay Control Register (ADPWRUPDLYCTRL) ....................................... 923
22.3.69 ADC Event Group Channel Selection Mode Control Register (ADEVCHNSELMODECTRL) ...... 924
22.3.70 ADC Group1 Channel Selection Mode Control Register (ADG1CHNSELMODECTRL) ............ 924
22.3.71 ADC Group2 Channel Selection Mode Control Register (ADG2CHNSELMODECTRL) ............ 925
22.3.72 ADC Event Group Current Count Register (ADEVCURRCOUNT) ..................................... 926
22.3.73 ADC Event Group Maximum Count Register (ADEVMAXCOUNT) .................................... 926
22.3.74 ADC Group1 Current Count Register (ADG1CURRCOUNT) ........................................... 927
22.3.75 ADC Group1 Maximum Count Register (ADG1MAXCOUNT) .......................................... 927
22.3.76 ADC Group2 Current Count Register (ADG2CURRCOUNT) ........................................... 928
22.3.77 ADC Group2 Maximum Count Register (ADG2MAXCOUNT) .......................................... 928
23 High-End Timer (N2HET) Module ........................................................................................ 929
23.1 Features.................................................................................................................... 930
23.1.1 Overview ......................................................................................................... 930
23.1.2 Block Diagram................................................................................................... 933
23.2 N2HET Functional Description.......................................................................................... 935
23.2.1 Specialized Timer Micromachine ............................................................................. 935
23.2.2 N2HET RAM Organization .................................................................................... 939
23.2.3 Time Base ....................................................................................................... 942
23.2.4 Host Interface ................................................................................................... 944
23.2.5 I/O Control ....................................................................................................... 945
23.2.6 Suppression Filters ............................................................................................. 960
23.2.7 Interrupts and Exceptions ..................................................................................... 960
23.2.8 Hardware Priority Scheme:.................................................................................... 961
23.2.9 N2HET Requests to DMA and HTU.......................................................................... 963
23.3 Angle Functions........................................................................................................... 964
23.3.1 Software Angle Generator..................................................................................... 964
23.4 N2HET Control Registers................................................................................................ 968
23.4.1 Global Configuration Register (HETGCR)................................................................... 969
23.4.2 Prescale Factor Register (HETPFR) ......................................................................... 970
23.4.3 N2HET Current Address Register (HETADDR) ............................................................ 971
23.4.4 Offset Index Priority Level 1 Register (HETOFF1) ......................................................... 971
23.4.5 Offset Index Priority Level 2 Register (HETOFF2) ......................................................... 972
23.4.6 Interrupt Enable Set Register (HETINTENAS).............................................................. 973
23.4.7 Interrupt Enable Clear Register (HETINTENAC) ........................................................... 973
23.4.8 Exception Control Register 1 (HETEXC1)................................................................... 974
23.4.9 Exception Control Register 2 (HETEXC2)................................................................... 975
23.4.10 Interrupt Priority Register (HETPRY) ....................................................................... 976
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Contents SPNU562–May 2014
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