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22.2.8 ADEVT Pin General Purpose I/O Functionality............................................................. 855
22.3 ADC Registers ............................................................................................................ 857
22.3.1 ADC Reset Control Register (ADRSTCR) .................................................................. 859
22.3.2 ADC Operating Mode Control Register (ADOPMODECR) ............................................... 859
22.3.3 ADC Clock Control Register (ADCLOCKCR) .............................................................. 861
22.3.4 ADC Calibration Mode Control Register (ADCALCR) ..................................................... 861
22.3.5 ADC Event Group Operating Mode Control Register (ADEVMODECR) ................................ 863
22.3.6 ADC Group1 Operating Mode Control Register (ADG1MODECR) ...................................... 866
22.3.7 ADC Group2 Operating Mode Control Register (ADG2MODECR) ...................................... 869
22.3.8 ADC Event Group Trigger Source Select Register (ADEVSRC) ......................................... 872
22.3.9 ADC Group1 Trigger Source Select Register (ADG1SRC) ............................................... 873
22.3.10 ADC Group2 Trigger Source Select Register (ADG2SRC).............................................. 874
22.3.11 ADC Event Interrupt Enable Control Register (ADEVINTENA) ......................................... 875
22.3.12 ADC Group1 Interrupt Enable Control Register (ADG1INTENA)....................................... 876
22.3.13 ADC Group2 Interrupt Enable Control Register (ADG2INTENA)....................................... 877
22.3.14 ADC Event Group Interrupt Flag Register (ADEVINTFLG).............................................. 878
22.3.15 ADC Group1 Interrupt Flag Register (ADG1INTFLG).................................................... 879
22.3.16 ADC Group2 Interrupt Flag Register (ADG2INTFLG).................................................... 880
22.3.17 ADC Event Group Threshold Interrupt Control Register (ADEVTHRINTCR) ......................... 881
22.3.18 ADC Group1 Threshold Interrupt Control Register (ADG1THRINTCR) ............................... 881
22.3.19 ADC Group2 Threshold Interrupt Control Register (ADG2THRINTCR) ............................... 882
22.3.20 ADC Event Group DMA Control Register (ADEVDMACR) .............................................. 883
22.3.21 ADC Group1 DMA Control Register (ADG1DMACR) .................................................... 885
22.3.22 ADC Group2 DMA Control Register (ADG2DMACR) .................................................... 887
22.3.23 ADC Results Memory Configuration Register (ADBNDCR) ............................................. 889
22.3.24 ADC Results Memory Size Configuration Register (ADBNDEND) ..................................... 890
22.3.25 ADC Event Group Sampling Time Configuration Register (ADEVSAMP)............................. 891
22.3.26 ADC Group1 Sampling Time Configuration Register (ADG1SAMP) ................................... 891
22.3.27 ADC Group2 Sampling Time Configuration Register (ADG2SAMP) ................................... 892
22.3.28 ADC Event Group Status Register (ADEVSR) ............................................................ 893
22.3.29 ADC Group1 Status Register (ADG1SR) .................................................................. 894
22.3.30 ADC Group2 Status Register (ADG2SR) .................................................................. 895
22.3.31 ADC Event Group Channel Select Register (ADEVSEL)................................................ 896
22.3.32 ADC Group1 Channel Select Register (ADG1SEL) ...................................................... 897
22.3.33 ADC Group2 Channel Select Register (ADG2SEL) ...................................................... 898
22.3.34 ADC Calibration and Error Offset Correction Register (ADCALR)...................................... 899
22.3.35 ADC State Machine Status Register (ADSMSTATE) .................................................... 899
22.3.36 ADC Channel Last Conversion Value Register (ADLASTCONV) ...................................... 900
22.3.37 ADC Event Group Results' FIFO Register (ADEVBUFFER) ............................................ 901
22.3.38 ADC Group1 Results FIFO Register (ADG1BUFFER)................................................... 902
22.3.39 ADC Group2 Results FIFO Register (ADG2BUFFER)................................................... 903
22.3.40 ADC Event Group Results Emulation FIFO Register (ADEVEMUBUFFER).......................... 904
22.3.41 ADC Group1 Results Emulation FIFO Register (ADG1EMUBUFFER) ................................ 905
22.3.42 ADC Group2 Results Emulation FIFO Register (ADG2EMUBUFFER) ................................ 906
22.3.43 ADC ADEVT Pin Direction Control Register (ADEVTDIR) .............................................. 907
22.3.44 ADC ADEVT Pin Output Value Control Register (ADEVTOUT) ........................................ 908
22.3.45 ADC ADEVT Pin Input Value Register (ADEVTIN)....................................................... 908
22.3.46 ADC ADEVT Pin Set Register (ADEVTSET) .............................................................. 909
22.3.47 ADC ADEVT Pin Clear Register (ADEVTCLR) ........................................................... 909
22.3.48 ADC ADEVT Pin Open Drain Enable Register (ADEVTPDR) .......................................... 910
22.3.49 ADC ADEVT Pin Pull Control Disable Register (ADEVTPDIS) ......................................... 910
22.3.50 ADC ADEVT Pin Pull Control Select Register (ADEVTPSEL) .......................................... 911
22.3.51 ADC Event Group Sample Cap Discharge Control Register (ADEVSAMPDISEN) .................. 911
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SPNU562–May 2014 Contents
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