Datasheet

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20.2.19 Transaction Errors ............................................................................................ 699
20.3 Control Registers and Control Packets ................................................................................ 700
20.3.1 Global Configuration Registers ............................................................................... 703
20.3.2 Channel Configuration ......................................................................................... 764
21 External Memory Interface (EMIF) ....................................................................................... 769
21.1 Introduction ................................................................................................................ 770
21.1.1 Purpose of the Peripheral ..................................................................................... 770
21.1.2 Features.......................................................................................................... 770
21.1.3 Functional Block Diagram ..................................................................................... 771
21.2 EMIF Module Architecture ............................................................................................... 772
21.2.1 EMIF Clock Control............................................................................................. 772
21.2.2 EMIF Requests.................................................................................................. 772
21.2.3 EMIF Signal Descriptions...................................................................................... 772
21.2.4 EMIF Signal Multiplexing Control ............................................................................. 773
21.2.5 SDRAM Controller and Interface ............................................................................. 774
21.2.6 Asynchronous Controller and Interface ...................................................................... 786
21.2.7 Data Bus Parking ............................................................................................... 798
21.2.8 Reset and Initialization Considerations ...................................................................... 799
21.2.9 Interrupt Support................................................................................................ 799
21.2.10 DMA Event Support........................................................................................... 800
21.2.11 EMIF Signal Multiplexing..................................................................................... 800
21.2.12 Memory Map................................................................................................... 800
21.2.13 Priority and Arbitration........................................................................................ 801
21.2.14 System Considerations....................................................................................... 802
21.2.15 Power Management .......................................................................................... 803
21.2.16 Emulation Considerations.................................................................................... 803
21.3 Registers................................................................................................................... 804
21.3.1 Module ID Register (MIDR) ................................................................................... 804
21.3.2 Asynchronous Wait Cycle Configuration Register (AWCC)............................................... 805
21.3.3 SDRAM Configuration Register (SDCR) .................................................................... 806
21.3.4 SDRAM Refresh Control Register (SDRCR)................................................................ 807
21.3.5 Asynchronous n Configuration Registers (CE2CFG-CE5CFG) .......................................... 808
21.3.6 SDRAM Timing Register (SDTIMR).......................................................................... 809
21.3.7 SDRAM Self Refresh Exit Timing Register (SDSRETR) .................................................. 810
21.3.8 EMIF Interrupt Raw Register (INTRAW)..................................................................... 811
21.3.9 EMIF Interrupt Masked Register (INTMSK) ................................................................. 812
21.3.10 EMIF Interrupt Mask Set Register (INTMSKSET) ........................................................ 813
21.3.11 EMIF Interrupt Mask Clear Register (INTMSKCLR)...................................................... 814
21.3.12 Page Mode Control Register (PMCR) ...................................................................... 815
21.4 Example Configuration................................................................................................... 816
21.4.1 Hardware Interface ............................................................................................. 816
21.4.2 Software Configuration......................................................................................... 816
22 Analog To Digital Converter (ADC) Module .......................................................................... 825
22.1 Overview .................................................................................................................. 826
22.1.1 Introduction ..................................................................................................... 827
22.2 Basic Operation ........................................................................................................... 829
22.2.1 Basic Features and Usage of the ADC ..................................................................... 829
22.2.2 Advanced Conversion Group Configuration Options ...................................................... 836
22.2.3 ADC Module Basic Interrupts ................................................................................ 844
22.2.4 ADC Module DMA Requests ................................................................................. 845
22.2.5 ADC Magnitude Threshold Interrupts ....................................................................... 846
22.2.6 ADC Special Modes............................................................................................ 847
22.2.7 ADC Results’ RAM Special Features ........................................................................ 854
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Contents SPNU562–May 2014
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