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19.4.2 VIM Input Channel Management ............................................................................. 651
19.5 Interrupt Vector Table (VIM RAM)...................................................................................... 652
19.5.1 Interrupt Vector Table Operation ............................................................................. 652
19.5.2 VIM ECC Syndrome............................................................................................ 653
19.5.3 Interrupt Vector Table Initialization ........................................................................... 654
19.5.4 Interrupt Vector Table ECC Testing.......................................................................... 654
19.6 VIM Wakeup Interrupt.................................................................................................... 656
19.7 Capture Event Sources .................................................................................................. 657
19.8 Examples .................................................................................................................. 657
19.8.1 Examples - Configure CPU To Receive Interrupts......................................................... 657
19.8.2 Examples - Register Vector Interrupt and Index Interrupt Handling ..................................... 658
19.9 VIM Control Registers.................................................................................................... 660
19.9.1 Interrupt Vector Table ECC Status Register (ECCSTAT) ................................................ 661
19.9.2 Interrupt Vector Table ECC Control Register (ECCCTL).................................................. 662
19.9.3 Uncorrectable Error Address Register (UERRADDR) ..................................................... 663
19.9.4 Fallback Vector Address Register (FBVECADDR)......................................................... 663
19.9.5 Single Bit Error Address Register (SBERRADDR)......................................................... 664
19.9.6 VIM Offset Vector Registers................................................................................... 664
19.9.7 IRQ Index Offset Vector Register (IRQINDEX)............................................................. 665
19.9.8 FIQ Index Offset Vector Registers (FIQINDEX) ............................................................ 665
19.9.9 FIQ/IRQ Program Control Registers (FIRQPR[0:3]) ....................................................... 666
19.9.10 Pending Interrupt Read Location Registers (INTREQ[0:3]) ............................................. 667
19.9.11 Interrupt Enable Set Registers (REQENASET[0:3])...................................................... 668
19.9.12 Interrupt Enable Clear Registers (REQENACLR[0:3]) ................................................... 669
19.9.13 Wake-Up Enable Set Registers (WAKEENASET[0:3])................................................... 670
19.9.14 Wake-Up Enable Clear Registers (WAKEENACLR[0:3]) ................................................ 671
19.9.15 IRQ Interrupt Vector Register (IRQVECREG)............................................................. 672
19.9.16 FIQ Interrupt Vector Register (FIQVECREG) ............................................................. 672
19.9.17 Capture Event Register (CAPEVT) ......................................................................... 673
19.9.18 VIM Interrupt Control Registers (CHANCTRL[0:31]) ..................................................... 674
20 Direct Memory Access Controller (DMA) Module .................................................................. 676
20.1 Overview ................................................................................................................... 677
20.1.1 Main Features................................................................................................... 677
20.1.2 System Resources Mapping .................................................................................. 678
20.2 Module Operation......................................................................................................... 679
20.2.1 Memory Space .................................................................................................. 680
20.2.2 DMA Data Access .............................................................................................. 680
20.2.3 Addressing Modes.............................................................................................. 681
20.2.4 DMA Channel Control Packets ............................................................................... 681
20.2.5 Priority Queue................................................................................................... 685
20.2.6 Data Packing and Unpacking ................................................................................. 687
20.2.7 DMA Request ................................................................................................... 690
20.2.8 Auto-Initiation.................................................................................................... 690
20.2.9 Interrupts......................................................................................................... 691
20.2.10 Debugging...................................................................................................... 693
20.2.11 Power Management .......................................................................................... 693
20.2.12 FIFO Buffer..................................................................................................... 694
20.2.13 Channel Chaining ............................................................................................. 695
20.2.14 Request Polarity............................................................................................... 695
20.2.15 Memory Protection ............................................................................................ 696
20.2.16 ECC Checking ................................................................................................. 697
20.2.17 ECC Testing ................................................................................................... 698
20.2.18 Initializing RAM with ECC .................................................................................... 698
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SPNU562–May 2014 Contents
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