Datasheet

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14 Oscillator and PLL ............................................................................................................ 498
14.1 Introduction ................................................................................................................ 499
14.1.1 Features.......................................................................................................... 499
14.2 Quick Start................................................................................................................. 500
14.3 Oscillator ................................................................................................................... 501
14.3.1 Oscillator Implementation...................................................................................... 502
14.3.2 Oscillator Enable................................................................................................ 502
14.3.3 Oscillator Disable ............................................................................................... 502
14.4 Low Power Oscillator and Clock Detect (LPOCLKDET)............................................................. 503
14.4.1 Clock Detect..................................................................................................... 503
14.4.2 Behavior on Oscillator Failure................................................................................. 503
14.4.3 Recovery from Oscillator Failure ............................................................................. 504
14.4.4 LPOCLKDET Enable ........................................................................................... 504
14.4.5 LPOCLKDET Disable .......................................................................................... 505
14.4.6 Trimming the HF LPO Oscillator.............................................................................. 505
14.5 PLL ......................................................................................................................... 506
14.5.1 Modulation ....................................................................................................... 508
14.5.2 PLL Output Control ............................................................................................. 509
14.5.3 Behavior on PLL Fail ........................................................................................... 512
14.5.4 Recovery from a PLL Failure.................................................................................. 513
14.5.5 PLL Modulation Depth Measurement ........................................................................ 514
14.5.6 PLL Frequency Measurement Circuit ........................................................................ 514
14.5.7 PLL2 .............................................................................................................. 514
14.6 Control Registers ......................................................................................................... 515
14.6.1 PLL Modulation Depth Measurement Control Register (SSWPLL1)..................................... 516
14.6.2 SSW PLL BIST Control Register 2 (SSWPLL2)............................................................ 517
14.6.3 SSW PLL BIST Control Register 3 (SSWPLL3)............................................................ 518
14.7 Phase-Locked Loop Theory of Operation ............................................................................. 519
14.7.1 Phase-Frequency Detector.................................................................................... 519
14.7.2 Charge Pump and Loop Filter................................................................................. 520
14.7.3 Voltage-Controlled Oscillator.................................................................................. 520
14.7.4 Frequency Modulation ......................................................................................... 521
14.8 Programming Example................................................................................................... 521
15 Dual-Clock Comparator (DCC) Module ................................................................................ 523
15.1 Introduction ................................................................................................................ 524
15.1.1 Main Features................................................................................................... 524
15.1.2 Block Diagram................................................................................................... 524
15.2 Module Operation......................................................................................................... 525
15.2.1 Single-Shot Measurement Mode ............................................................................. 528
15.3 Clock Source Selection for Counter0 and Counter1 ................................................................. 529
15.4 DCC Control Registers................................................................................................... 530
15.4.1 DCC Global Control Register (DCCGCTRL) ............................................................... 531
15.4.2 DCC Revision Id Register (DCCREV) ...................................................................... 532
15.4.3 DCC Counter0 Seed Register (DCCCNT0SEED) ......................................................... 532
15.4.4 DCC Valid0 Seed Register (DCCVALID0SEED) .......................................................... 533
15.4.5 DCC Counter1 Seed Register (DCCCNT1SEED) ......................................................... 533
15.4.6 DCC Status Register (DCCSTAT) ........................................................................... 534
15.4.7 DCC Counter0 Value Register (DCCCNT0) ................................................................ 535
15.4.8 DCC Valid0 Value Register (DCCVALID0) ................................................................. 536
15.4.9 DCC Counter1 Value Register (DCCCNT1) ................................................................ 536
15.4.10 DCC Counter1 Clock Source Selection Register (DCCCNT1CLKSRC) .............................. 537
15.4.11 DCC Counter0 Clock Source Selection Register (DCCCNT0CLKSRC) .............................. 537
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SPNU562–May 2014 Contents
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