Datasheet

www.ti.com
9.5.10 ROM Mask Register (ROM) ................................................................................... 405
9.5.11 ROM Algorithm Mask Register (ALGO) ..................................................................... 406
9.5.12 RAM Info Mask Lower Register (RINFOL) .................................................................. 407
9.5.13 RAM Info Mask Upper Register (RINFOU).................................................................. 408
9.6 PBIST Configuration Example .......................................................................................... 409
9.6.1 Example 1 : Configuration of PBIST Controller to Run Self-Test on DCAN1 RAM..................... 409
9.6.2 Example 2 : Configuration of PBIST Controller to Run Self-Test on ALL RAM Groups................ 410
10 Self-Test Controller (STC) Module....................................................................................... 411
10.1 General Description ...................................................................................................... 412
10.1.1 Self-Test Controller Features ................................................................................. 412
10.1.2 Terminology ..................................................................................................... 413
10.1.3 STC Block Diagram ............................................................................................ 413
10.2 STC Module Assignments ............................................................................................... 419
10.3 STC Programmers Flow ................................................................................................. 420
10.4 Application Self-Test Flow ............................................................................................... 421
10.4.1 STC Module Configuration .................................................................................... 421
10.4.2 Context Saving - CPU.......................................................................................... 421
10.4.3 Entering CPU Idle Mode ....................................................................................... 422
10.4.4 Entering nHET Idle Mode...................................................................................... 422
10.4.5 Self-Test Completion and Error Generation................................................................. 422
10.5 STC1 Segment 0 (CPU) Test Coverage and Duration .............................................................. 424
10.6 STC1 Segment 1 (uSCU) Test Coverage and Duration............................................................. 426
10.7 STC2 (nHET) Test Coverage and Duration ........................................................................... 427
10.8 STC Control Registers ................................................................................................... 428
10.8.1 STC Global Control Register 0 (STCGCR0) ................................................................ 429
10.8.2 STC Global Control Register 1 (STCGCR1) ................................................................ 430
10.8.3 Self-Test Run Timeout Counter Preload Register (STCTPR) ............................................ 430
10.8.4 STC Current ROM Address Register - CORE1 (STCCADDR1) ......................................... 431
10.8.5 STC Current Interval Count Register (STCCICR).......................................................... 431
10.8.6 Self-Test Global Status Register (STCGSTAT) ............................................................ 432
10.8.7 Self-Test Fail Status Register (STCFSTAT) ................................................................ 433
10.8.8 CORE1 Current MISR Registers (CORE1_CURMISR[3:0]) .............................................. 434
10.8.9 CORE2 Current MISR Registers (CORE2_CURMISR[3:0]) .............................................. 435
10.8.10 Signature Compare Self-Check Register (STCSCSCR) ................................................. 436
10.8.11 STC Current ROM Address Register - CORE2 (STCCADDR2) ........................................ 436
10.8.12 STC Clock Prescalar Register (STCCLKDIV) ............................................................. 437
10.8.13 Segment Interval Preload Register (STCSEGPLR) ...................................................... 438
10.9 STC Configuration Example............................................................................................. 439
10.9.1 Example: STC1 Self-Test Run ................................................................................ 439
10.10 Self-Test Controller Diagnostics ........................................................................................ 440
11 System Memory Protection Unit (NMPU).............................................................................. 441
11.1 Overview ................................................................................................................... 442
11.1.1 Features.......................................................................................................... 442
11.1.2 Safety Diagnostic ............................................................................................... 442
11.1.3 Block Diagram................................................................................................... 443
11.2 Module Operation......................................................................................................... 444
11.2.1 Functional Mode ................................................................................................ 444
11.2.2 Diagnostic Mode ................................................................................................ 446
11.2.3 Functional Fail Safe ............................................................................................ 446
11.3 How to Use NMPU ....................................................................................................... 447
11.3.1 How to Use NMPU in Functional Mode...................................................................... 447
11.3.2 How to Use Diagnostics ....................................................................................... 449
11.4 NMPU Registers .......................................................................................................... 452
7
SPNU562–May 2014 Contents
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated