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7.11.28 Lower Word of Reset Configuration Read Register (RCR_VALUE0) .................................. 362
7.11.29 Upper Word of Reset Configuration Read Register (RCR_VALUE1) .................................. 362
7.11.30 FSM Register Write Enable Register (FSM_WR_ENA).................................................. 363
7.11.31 EEPROM Emulation Configuration Register (EEPROM_CONFIG) .................................... 363
7.11.32 FSM Sector Register 1 (FSM_SECTOR1)................................................................. 364
7.11.33 FSM Sector Register 2 (FSM_SECTOR2)................................................................. 364
7.11.34 Flash Bank Configuration Register (FCFG_BANK)....................................................... 365
7.12 POM Control Registers .................................................................................................. 366
7.12.1 POM Global Control Register (POMGLBCTRL)............................................................ 366
7.12.2 POM Revision ID Register (POMREV) ...................................................................... 367
7.12.3 POM Flag Register (POMFLG) ............................................................................... 367
7.12.4 POM Region Start Address Register (POMPROGSTARTx).............................................. 368
7.12.5 POM Overlay Region Start Address Register (POMOVLSTARTx) ...................................... 368
7.12.6 POM Region Size Register (POMREGSIZEx).............................................................. 369
8 Level 2 RAM (L2RAMW) Module ......................................................................................... 370
8.1 Overview ................................................................................................................... 371
8.2 Module Operation......................................................................................................... 371
8.2.1 RAM Memory Map............................................................................................... 371
8.2.2 Safety Features .................................................................................................. 372
8.2.3 L2RAMW Auto-Initialization .................................................................................... 375
8.2.4 Trace Module Support .......................................................................................... 375
8.2.5 Emulation/Debug Mode Behavior.............................................................................. 375
8.2.6 Diagnostic Test Procedure ..................................................................................... 375
8.3 Control and Status Registers............................................................................................ 376
8.3.1 L2RAMW Module Control Register (RAMCTRL) ............................................................ 376
8.3.2 L2RAMW Error Status Register (RAMERRSTATUS)....................................................... 378
8.3.3 L2RAMW Diagnostic Data Vector High Register (DIAG_DATA_VECTOR_H) .......................... 381
8.3.4 L2RAMW Diagnostic Data Vector Low Register (DIAG_DATA_VECTOR_L) ........................... 381
8.3.5 L2RAMW Diagnostic ECC Vector Register (DIAG_ECC) .................................................. 382
8.3.6 L2RAMW RAM Test Mode Control Register (RAMTEST) ................................................. 383
8.3.7 L2RAMW RAM Address Decode Vector Test Register (RAMADDRDEC_VECT) ...................... 384
8.3.8 L2RAMW Memory Initialization Domain Register (MEMINIT_DOMAIN) ................................. 385
8.3.9 L2RAMW Bank to Domain Mapping Register0 (BANK_DOMAIN_MAP0) ............................... 386
8.3.10 L2RAMW Bank to Domain Mapping Register1 (BANK_DOMAIN_MAP1).............................. 386
9 Programmable Built-In Self-Test (PBIST) Module.................................................................. 388
9.1 Overview ................................................................................................................... 389
9.1.1 Features of PBIST ............................................................................................... 389
9.1.2 PBIST vs. Application Software-Based Testing.............................................................. 389
9.1.3 PBIST Block Diagram ........................................................................................... 389
9.2 RAM Grouping and Algorithm........................................................................................... 390
9.3 PBIST Flow ................................................................................................................ 391
9.3.1 PBIST Sequence................................................................................................. 392
9.4 Memory Test Algorithms on the On-chip ROM ...................................................................... 394
9.5 PBIST Control Registers ................................................................................................ 395
9.5.1 RAM Configuration Register (RAMT) ......................................................................... 396
9.5.2 Datalogger Register (DLR) ..................................................................................... 397
9.5.3 PBIST Activate/ROM Clock Enable Register (PACT)....................................................... 398
9.5.4 PBIST ID Register ............................................................................................... 399
9.5.5 Override Register (OVER)...................................................................................... 400
9.5.6 Fail Status Fail Registers (FSRF0 and FSRF1) ............................................................. 401
9.5.7 Fail Status Count Registers (FSRC0 and FSRC1).......................................................... 402
9.5.8 Fail Status Address Registers (FSRA0 and FSRA1) ....................................................... 403
9.5.9 Fail Status Data Registers (FSRDL0 and FSRDL1) ........................................................ 404
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Contents SPNU562–May 2014
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