Datasheet
www.ti.com
5.4.5 Power Domain Clock Disable Clear Register (PDCLKDISCLRREG)..................................... 275
5.4.6 Logic Power Domain PD2 Power Status Register (LOGICPDPWRSTAT0) ............................. 276
5.4.7 Logic Power Domain PD3 Power Status Register (LOGICPDPWRSTAT1) ............................. 277
5.4.8 Logic Power Domain PD4 Power Status Register (LOGICPDPWRSTAT2) ............................. 278
5.4.9 Logic Power Domain PD5 Power Status Register (LOGICPDPWRSTAT3) ............................. 279
5.4.10 Logic Power Domain PD6 Power Status Register (LOGICPDPWRSTAT4) ............................ 280
5.4.11 Global Control Register 1 (GLOBALCTRL1)................................................................ 281
5.4.12 Global Status Register (GLOBALSTAT)..................................................................... 282
5.4.13 PSCON Diagnostic Compare Key Register (PRCKEYREG) ............................................. 282
5.4.14 LogicPD PSCON Diagnostic Compare Status Register 1 (LPDDCSTAT1)............................. 283
5.4.15 LogicPD PSCON Diagnostic Compare Status Register 2 (LPDDCSTAT2)............................. 284
5.4.16 Isolation Diagnostic Status Register (ISODIAGSTAT)..................................................... 285
6 I/O Multiplexing and Control Module (IOMM) ........................................................................ 286
6.1 Overview .................................................................................................................. 287
6.2 Main Features of I/O Multiplexing Module (IOMM)................................................................... 287
6.3 Control of Multiplexed Outputs.......................................................................................... 287
6.4 Control of Multiplexed Inputs............................................................................................ 288
6.5 Control of Special Multiplexed Options ................................................................................ 297
6.5.1 Control of SDRAM clock (EMIF_CLK) ........................................................................ 299
6.5.2 Control for other EMIF Outputs ................................................................................ 299
6.5.3 Control of Ethernet Controller Mode .......................................................................... 299
6.5.4 Control of ADC Trigger Events................................................................................. 299
6.5.5 Control for ADC Event Trigger Signal Generation from ePWMx Modules ............................... 300
6.5.6 Control for Generating Interrupt Upon External Fault Indication to N2HETx ............................ 303
6.5.7 Control for Synchronizing Time Bases for All ePWMx Modules........................................... 305
6.5.8 Control for Synchronizing all ePWMx Modules to N2HET1 Module Time-Base ........................ 305
6.5.9 Control for Input Connections to ePWMx Modules.......................................................... 306
6.5.10 Control for Input Connections to eCAPx Modules.......................................................... 307
6.5.11 Control for Input Connections to eQEPx Modules.......................................................... 308
6.5.12 Selecting GIO Port for External DMA Request ............................................................. 310
6.5.13 Temperature Sensor Selection ............................................................................... 311
6.6 Safety Features ........................................................................................................... 312
6.6.1 Locking Mechanism for Memory-Mapped Registers ........................................................ 312
6.6.2 Master ID Check ................................................................................................. 312
6.6.3 Error Conditions.................................................................................................. 312
6.7 IOMM Registers........................................................................................................... 313
6.7.1 REVISION_REG: Revision Register .......................................................................... 313
6.7.2 BOOT_REG: Boot Mode Register............................................................................. 314
6.7.3 KICK_REG0: Kicker Register 0 ................................................................................ 314
6.7.4 KICK_REG1: Kicker Register 1 ................................................................................ 314
6.7.5 ERR_RAW_STATUS_REG: Error Raw Status / Set Register............................................. 315
6.7.6 ERR_ENABLED_STATUS_REG: Error Enabled Status / Clear Register................................ 316
6.7.7 ERR_ENABLE_REG: Error Signaling Enable Register..................................................... 317
6.7.8 ERR_ENABLE_CLR_REG: Error Signaling Enable Clear Register ...................................... 318
6.7.9 FAULT_ADDRESS_REG: Fault Address Register.......................................................... 318
6.7.10 FAULT_STATUS_REG: Fault Status Register ............................................................. 319
6.7.11 FAULT_CLEAR_REG: Fault Clear Register ................................................................ 320
6.7.12 PINMMRnn: Output Pin Multiplexing Control Registers ................................................... 320
6.7.13 PINMMRnn: Input Pin Multiplexing Control Registers ..................................................... 321
6.7.14 PINMMRnn: Special Functionality Multiplexing Control Registers ....................................... 321
7 F021 Level 2 Flash Module Controller (L2FMC)..................................................................... 322
7.1 Overview ................................................................................................................... 323
7.1.1 Features........................................................................................................... 323
4
Contents SPNU562–May 2014
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated