Datasheet
Contents
Preface....................................................................................................................................... 94
1 Introduction....................................................................................................................... 95
1.1 Designed for Safety Applications......................................................................................... 96
1.2 Family Description.......................................................................................................... 97
1.3 Endianism Considerations............................................................................................... 100
1.3.1 RM57Lx: Little Endian (LE)..................................................................................... 100
2 Architecture ..................................................................................................................... 101
2.1 Introduction ................................................................................................................ 102
2.1.1 Architecture Block Diagram .................................................................................... 102
2.1.2 Definitions of Terms ............................................................................................. 104
2.1.3 Bus Master / Slave Access Privileges ........................................................................ 107
2.1.4 CPU Interconnect Subsystem SDC MMR Port .............................................................. 107
2.1.5 Interconnect Subsystem Runtime Status ..................................................................... 108
2.1.6 Master ID to PCRx............................................................................................... 108
2.2 Memory Organization .................................................................................................... 109
2.2.1 Memory Map Overview ......................................................................................... 109
2.2.2 Memory Map Table .............................................................................................. 111
2.2.3 Flash on Microcontrollers ....................................................................................... 117
2.2.4 On-Chip SRAM................................................................................................... 122
2.3 Exceptions ................................................................................................................. 127
2.3.1 Resets............................................................................................................. 127
2.3.2 Aborts ............................................................................................................. 127
2.3.3 System Software Interrupts..................................................................................... 129
2.4 Clocks ...................................................................................................................... 130
2.4.1 Clock Sources.................................................................................................... 130
2.4.2 Clock Domains ................................................................................................... 131
2.4.3 Low Power Modes ............................................................................................... 133
2.4.4 Clock Test Mode ................................................................................................. 134
2.4.5 Embedded Trace Macrocell (ETM-R5)........................................................................ 136
2.4.6 Safety Considerations for Clocks .............................................................................. 136
2.5 System and Peripheral Control Registers ............................................................................. 139
2.5.1 Primary System Control Registers (SYS) .................................................................... 139
2.5.2 Secondary System Control Registers (SYS2) ............................................................... 191
2.5.3 Peripheral Central Resource (PCR) Control Registers .................................................... 203
3 SCR Control Module (SCM)................................................................................................ 237
3.1 Overview ................................................................................................................... 238
3.1.1 Features........................................................................................................... 238
3.1.2 System Block Diagram .......................................................................................... 239
3.2 Module Operation......................................................................................................... 240
3.2.1 Block Diagram.................................................................................................... 240
3.2.2 Timeout Threshold Compare Block ........................................................................... 240
3.2.3 SCM Control Block .............................................................................................. 241
3.3 How to Use SCM ......................................................................................................... 242
3.3.1 How to Check the Parity Compare Logic ..................................................................... 242
3.3.2 How to Initiate Self-test Sequence ............................................................................ 243
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Contents SPNU562–May 2014
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