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37.4 eFuse Controller Registers
All registers in the eFuse Controller module are 32-bit, word-aligned; 8-bit, 16-bit and 32-bit accesses are
allowed. Table 37-2 provides a quick reference to each of these registers. Specific bit descriptions are
discussed in the following subsections. The base address for the control registers is FFF8 C000h.
Table 37-2. eFuse Controller Registers
Offset Acronym Register Description Section
FFF8 C01Ch EFCBOUND EFC Boundary Control Register Section 37.4.1
FFF8 C02Ch EFCPINS EFC Pins Register Section 37.4.2
FFF8 C03Ch EFC_ERR_STAT EFC Error Status Register Section 37.4.3
FFF8 C048h EFC_ST_CY EFC Self Test Cycles Register Section 37.4.4
FFF8 C04Ch EFC_ST_SIG EFC Self Test Signature Register Section 37.4.5
37.4.1 EFC Boundary Control Register (EFCBOUND)
Figure 37-2 and Table 37-3 describe the EFCBOUND register. The eFuse Boundary Control Register is
used to test the connections between the eFuse controller and the ESM module. The eFuse Boundary
Control Register is also used to initiate an eFuse controller ECC self-test.
Figure 37-2. EFC Boundary Control Register (EFCBOUND) [offset = 1Ch]
31 24
Reserved
R-0
23 22 21 20 19 18 17 16
Reserved EFC Self Test EFC Single Bit EFC Instruction EFC Autoload Self Test Single Bit
Error Error Error Error Error OE Error OE
R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15 14 13 12 8
Instruction Autoload EFC ECC Selftest Reserved
Error OE Error OE Enable
R/W-0 R/W-0 R/W-0 R-0
7 4 3 0
Reserved Input Enable
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after power-on reset (nPORRST)
Table 37-3. EFC Boundary Register (EFCBOUND) Field Descriptions
Bit Field Value Description
31-22 Reserved 0 Read returns 0. Writes have no effect.
21 EFC Self Test Error This bit drives the self test error signal when bit 17 (Self Test Error OE) is high. This signal
is attached to ESM error Group 1, Channel 41.
0 Drives the self test error signal low if Self Test OE is high
1 Drives the self test error signal high if Self Test OE is high
20 EFC Single Bit Error This bit drives the single bit error signal when bit 16 (Single bit Error OE) is high. This signal
is attached to ESM error Group 1, Channel 40.
0 Drives the self test error signal low if Single Bit Error OE is high
1 Drives the self test error signal high if Single Bit Error OE is high
1908
eFuse Controller SPNU562–May 2014
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