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RTP Control Registers

36.3.10 RTP Pin Control 1 Register (RTPPC1)

Once the pin is configured in functional mode (using RTPPC0 register), configuring the corresponding bit

in RTPPC1 to 0 will not disable the output driver. Figure 36-18 and Table 36-19 describe this register.

Figure 36-18. RTP Pin Control 1 Register (RTPPC1) (offset = 38h)

31 19 18 17 16

Reserved ENADIR CLKDIR SYNCDIR

R-0 R/W-0 R/W-0 R/W-0

15 0

DATADIR[15:0]

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 36-19. RTP Pin Control 1 Register (RTPPC1) Field Descriptions

Bit Field Value Description

31-19 Reserved 0 Read returns 0. Writes have no effect.

18 ENADIR Direction of RTPENA pin. This bit defines whether the pin is used as input or output in GIO mode.

This bit has no effect when the pin is configured in functional mode.

Read:

0 Pin is used as input.

1 Pin is used as output.

Write:

0 Configure pin to input mode.

1 Configure pin to output mode.

17 CLKDIR Direction of RTPCLK pin. This bit defines whether the pin is used as input or output in GIO mode.

This bit has no effect when the pin is configured in functional mode.

Read:

0 Pin is used as input.

1 Pin is used as output.

Write:

0 Configure pin to input mode.

1 Configure pin to output mode.

16 SYNCDIR Direction of RTPSYNC pin. This bit defines whether the pin is used as input or output in GIO mode.

This bit has no effect when the pin is configured in functional mode.

Read:

0 Pin is used as input.

1 Pin is used as output.

Write:

0 Configure pin to input mode.

1 Configure pin to output mode.

15-0 DATADIR[n] Direction of RTPDATA[15:0] pins. These bits define whether the pins are used as input or output in

GIO mode. These bits have no effect when the pins are configured in functional mode. Each bit [n]

represents a single pin.

Read:

0 Pin is used as input.

1 Pin is used as output.

Write:

0 Configure pin to input mode.

1 Configure pin to output mode.

1895

SPNU562–May 2014 RAM Trace Port (RTP)

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