Datasheet

211
RM57L843
www.ti.com SPNS215C –FEBRUARY 2014–REVISED JUNE 2016
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9.6 Device Identification
9.6.1 Device Identification Code Register
The device identification code register is memory mapped to address FFFF FFF0h and identifies several
aspects of the device including the silicon version. The details of the device identification code register are
provided in Table 9-1. The device identification code register value for this device is:
• Rev A = 0x8044AD05
• Rev B = 0x8044AD0D
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CP-15 UNIQUE ID TECH
R-1 R-00000000100010 R-0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TECH
I/O
VOLTAGE
PERIPH
PARITY
FLASH ECC
RAM
ECC
VERSION 1 0 1
R-101 R-0 R-1 R-10 R-1 R-00000 R-1 R-0 R-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 9-2. Device ID Bit Allocation Register
Table 9-1. Device ID Bit Allocation Register Field Descriptions
Bit Field Value Description
31 CP15 Indicates the presence of coprocessor 15
1 CP15 present
30-17 UNIQUE ID 100011
Silicon version (revision) bits.
This bitfield holds a unique number for a dedicated device configuration (die).
16-13 TECH Process technology on which the device is manufactured.
0101 F021
12 I/O VOLTAGE I/O voltage of the device.
0 I/O are 3.3v
11 PERIPHERAL
PARITY
Peripheral Parity
1 Parity on peripheral memories
10-9 FLASH ECC Flash ECC
10 Program memory with ECC
8 RAM ECC Indicates if RAM ECC is present.
1 ECC implemented
7-3 REVISION Revision of the Device.
2-0 101 The platform family ID is always 0b101