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Module Operation

Table 36-1. Encoding of RAM Bits in Trace Mode Packet Format

RAM[1:0] RAM

0 Level 2 lower 256kB RAM

1h Level 2 upper 256kB RAM

2h Peripherals under PCR1

3h Peripherals under PCR3

Table 36-2. Encoding of Status Bits in Trace Mode Packet Format

STAT[1:0] Status

0 Normal entry CPU1

1h Normal entry other Master

2h Normal entry CPU2

3h Overflow of the dedicated FIFO

In the event of a FIFO overflow, an overflow will be signaled in the status bits of the next transmitted

packet of that particular FIFO. The last entry in the FIFO will not be overwritten by the new data.

Table 36-3. Encoding of SIZE bits in Trace Mode Packet Format

SIZE[1:0] Write/Read Size

0 8 bit

1h 16 bit

2h 32 bit

3h 64 bit

Table 36-4. Encoding of REG in Trace Mode Packet Format

REG Region

0 1

1 2

The packet will be split up into several subpackets when transmitted over the RTP port pins depending on

the port width configured. The port width is configured with bits PW[1:0] in the RTPGLBCTRL register

(Section 36.3.1). For certain port width configurations and write/read sizes, the number of bits in a packet

does not exactly match the port width for the last subpacket. The remaining bits will be filled with zeros.

Table 36-5. Number of Transfers/Packet

Write/Read Size in bits

Port Width 8 16 32 64

2 16 --> 16 20 --> 20 28 --> 28 44 --> 44

4 8 --> 8 10 --> 10 14 --> 14 22 --> 22

8 4 --> 4 5 --> 5 7 --> 7 11 --> 11

16 2 --> 2 2.5 --> 3 3.5 --> 4 5.5 --> 6

1875

SPNU562–May 2014 RAM Trace Port (RTP)

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