Datasheet

Per1

Per2

PerN

Per1

Per2

PerN

PCR1 PCR3

Lower

256k

L2 SRAM

Upper

256k

L2 SRAM

CPU Interconnect Subsystem Peripheral Interconnect Subsystem

CPU

FIFO1

FIFO2

FIFO3

FIFO4

RAM Trace Port

SERIALIZER

RTPENA

RTPSYNC

RTPCLK

RTPDATA[x]

RTPDATA[0]

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Overview

36.1.2 Block Diagram

Figure 36-1 is a block diagram of the RTP.

Figure 36-1. RAM Trace Port Module Block Diagram

1873

SPNU562–May 2014 RAM Trace Port (RTP)

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