Datasheet
Control Registers
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35.3.19 DMM Pin Control 3 (DMMPC3)
The bits in this register set the pin to logic low or high level if the pin is configured as output
(Section 35.3.17).
Figure 35-25. DMM Pin Control 3 (DMMPC3) [offset = 78h]
31 24
Reserved
R-0
23 19 18 17 16
Reserved ENAOUT DATA15OUT DATA14OUT
R-0 R/W-0 R/W-0 R/W-0
15 14 13 12 11 10 9 8
DATA13OUT DATA12OUT DATA11OUT DATA10OUT DATA9OUT DATA8OUT DATA7OUT DATA6OUT
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7 6 5 4 3 2 1 0
DATA5OUT DATA4OUT DATA3OUT DATA2OUT DATA1OUT DATA0OUT CLKOUT SYNCOUT
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 35-25. DMM Pin Control 3 (DMMPC3) Field Descriptions
Bit Field Value Description
31-19 Reserved 0 Reads returns 0. Writes have no effect.
18 ENAOUT Output state of DMMENA pin. This bit sets the pin to logic low or high level
User and privilege mode (read):
0 Logic low (output voltage is V
OL
or lower)
1 Logic high (output voltage is V
OH
or higher)
User and privilege mode (write):
0 Logic low (output voltage is set to V
OL
or lower)
1 Logic high (output voltage is set to V
OH
or higher)
17-2 DATAxOUT Output state of DMMDATA[x] pin. This bit sets the pin to logic low or high level.
User and privilege mode (read):
0 Logic low (output voltage is V
OL
or lower)
1 Logic high (output voltage is V
OH
or higher)
User and privilege mode (write):
0 Logic low (output voltage is set to V
OL
or lower)
1 Logic high (output voltage is set to V
OH
or higher)
1 CLKOUT Output state of DMMCLK pin. This bit sets the pin to logic low or high level
User and privilege mode (read):
0 Logic low (output voltage is V
OL
or lower)
1 Logic high (output voltage is V
OH
or higher)
User and privilege mode (write):
0 Logic low (output voltage is set to V
OL
or lower)
1 Logic high (output voltage is set to V
OH
or higher)
1862
Data Modification Module (DMM) SPNU562–May 2014
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