Datasheet
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Control Registers
35.3.18 DMM Pin Control 2 (DMMPC2)
The bits in this register reflect the digital representation of the voltage level at the module pins. Even if a
pin is configured to be an output pin, the level can be read back via this register.
Figure 35-24. DMM Pin Control 2 (DMMPC2) [offset = 74h]
31 24
Reserved
R-0
23 19 18 17 16
Reserved ENAIN DATA15IN DATA14IN
R-0 R/W-0 R/W-0 R/W-0
15 14 13 12 11 10 9 8
DATA13IN DATA12IN DATA11IN DATA10IN DATA9IN DATA8IN DATA7IN DATA6IN
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7 6 5 4 3 2 1 0
DATA5IN DATA4IN DATA3IN DATA2IN DATA1IN DATA0IN CLKIN SYNCIN
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 35-24. DMM Pin Control 2 (DMMPC2) Field Descriptions
Bit Field Value Description
31-19 Reserved 0 Reads returns 0. Writes have no effect.
18 ENAIN DMMENA input. This bit reflects the state of the pin in all modes.
User and privilege mode (read):
0 Logic low (input voltage is V
IL
or lower)
1 Logic high (input voltage is V
IH
or higher)
Privilege mode (write): writes to this bit have no effect.
17-2 DATAxIN DMMDATA[x] input. This bit reflects the state of the pin in all modes.
User and privilege mode (read):
0 Logic low (input voltage is V
IL
or lower)
1 Logic high (input voltage is V
IH
or higher)
Privilege mode (write): writes to this bit have no effect.
1 CLKIN DMMCLK input. This bit reflects the state of the pin in all modes.
User and privilege mode (read):
0 Logic low (input voltage is V
IL
or lower)
1 Logic high (input voltage is V
IH
or higher)
Privilege mode (write): writes to this bit have no effect.
0 SYNCIN DMMSYNC input. This bit reflects the state of the pin in all modes
User and privilege mode (read):
0 Logic low (input voltage is V
IL
or lower)
1 Logic high (input voltage is V
IH
or higher)
Privilege mode (write): writes to this bit have no effect.
1861
SPNU562–May 2014 Data Modification Module (DMM)
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