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Control Registers

35.3.15 DMM Destination x Blocksize 2 (DMMDESTxBL2)

This register defines the blocksize of the buffer used to store the received data in Trace Mode. If the

received data does not fall into the address range defined by DMMDESTxREG2 and DMMDESTxBL2, an

interrupt (DESTx_ERR) can be generated. The description below is valid for following registers:

DMMDEST0BL2, DMMDEST1BL2, DMMDEST2BL2, DMMDEST3BL2.

Figure 35-21. DMM Destination x Blocksize 2 (DMMDESTxBL2) [offset = 38h, 48h, 58h, 68h]

31 16

Reserved

R-0

15 4 3 0

Reserved BLOCKSIZE

R-0 R/WP-0

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset

Table 35-21. DMM Destination x Blocksize 2 (DMMDESTxBL2) Field Descriptions

Bit Field Value Description

31-4 Reserved 0 Read returns 0. Writes have no effect.

3-0 BLOCKSIZE These bits define the length of the buffer region. If all bits are 0, the region is disabled and

no data will be stored.

User and privilege mode (read): current block size

Privilege mode (write):

0 Region disabled

1h 1 KByte

2h 2 KByte

3h 4 KByte

4h 8 KByte

5h 16 KByte

6h 32 KByte

7h 64 KByte

8h 128 KByte

9h 256 KByte

Ah-Fh Reserved

1857

SPNU562–May 2014 Data Modification Module (DMM)

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