Datasheet

Control Registers

www.ti.com

35.3.14 DMM Destination x Region 2 (DMMDESTxREG2)

This register defines the starting address of the buffer used to store the received data in Trace Mode. If

the received data does not fall into the address range defined by DMMDESTxREG2 and DMMDESTxBL2,

an interrupt (DESTx_ERR) can be generated. The description below is valid for following registers:

DMMDEST0REG2, DMMDEST1REG2, DMMDEST2REG2, DMMDEST3REG2.

Figure 35-20. DMM Destination x Region 2 (DMMDESTxREG2) [offset = 34h, 44h, 54h, 64h]

31 18 17 16

BASEADDR BLOCKADDR

R/WP-0 R/WP-0

15 0

BLOCKADDR

R/WP-0

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset

Table 35-20. DMM Destination x Region 2 (DMMDESTxREG2) Field Descriptions

Bit Field Description

31-18 BASEADDR These bits define the base address of the 256kB region where the buffer is located.

User and privilege mode (read): current start address

Privilege mode (write): sets base address to value written

17-0 BLOCKADDR These bits define the starting address of the buffer in the 256kB page. The starting address has to be a

multiple of the blocksize chosen in DMMDESTxBL1 (Section 35.3.15).

User and privilege mode (read): current start address

Privilege mode (write): sets start address to value written

1856

Data Modification Module (DMM) SPNU562–May 2014

Submit Documentation Feedback