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35.3.6 DMM Interrupt Offset 1 Register (DMMOFF1)
This register holds the offset indicating which interrupt occurred on interrupt level 0. The CPU can read
this register to determine the source of the interrupt without having to test individual interrupt flags.
Figure 35-12. DMM Interrupt Offset 1 Register (DMMOFF1) [offset = 14h]
31 16
Reserved
R-0
15 5 4 0
Reserved OFFSET
R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 35-12. DMM Interrupt Offset 1 Register (DMMOFF1) Field Descriptions
Bit Field Value Description
31-5 Reserved 0 Read returns 0. Writes have no effect.
4-0 OFFSET User and privilege mode (read):
Bit Encoding Interrupt
0 Phantom. All interrupt flags have been cleared before the offset register has been read.
1h Packet Error
2h Destination 0 Error
3h Destination 1 Error
4h Destination 2 Error
5h Destination 3 Error
6h Source Overflow
7h Buffer Overflow
8h Bus Error
9h Destination 0 Region 1
Ah Destination 0 Region 2
Bh Destination 1 Region 1
Ch Destination 1 Region 2
Dh Destination 2 Region 1
Eh Destination 2 Region 2
Fh Destination 3 Region 1
10h Destination 3 Region 2
11h End of Buffer
12h Programmable Buffer
13h-1Fh Reserved
Reading the offset will clear the corresponding flag in DMMINTFLG (Section 35.3.5).
Privilege and user mode writes have no effect
1850
Data Modification Module (DMM) SPNU562–May 2014
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