Datasheet

Control Registers www.ti.com
35.3.5 DMM Interrupt Flag Register (DMMINTFLG)
This register contains the interrupt level bits for error interrupts and normal interrupts.
Figure 35-11. DMM Interrupt Flag Register (DMMINTFLG) [offset = 10h]
31 24
Reserved
R-0
23 18 17 16
Reserved PROG_BUFF EO_BUFF
R-0 R/WPC-0 R/WPC-0
15 14 13 12 11 10 9 8
DEST3REG2 DEST3REG1 DEST2REG2 DEST2REG1 DEST1REG2 DEST1REG1 DEST0REG2 DEST0REG1
R/WPC-0 R/WPC-0 R/WPC-0 R/WPC-0 R/WPC-0 R/WPC-0 R/WPC-0 R/WPC-0
7 6 5 4 3 2 1 0
BUSERROR BUFF_OVF SRC_OVF DEST3_ERR DEST2_ERR DEST1_ERR DEST0_ERR PACKET_ERR_INT
R/WPC-0 R/WPC-0 R/WPC-0 R/WPC-0 R/WPC-0 R/WPC-0 R/WPC-0 R/WPC-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; C = Clear; -n = value after reset
Table 35-11. DMM Interrupt Flag Register (DMMINTFLG) Field Descriptions
Bit Field Value Description
31-18 Reserved 0 Reads returns 0. Writes have no effect.
17 PROG_BUFF Programmable Buffer Interrupt Flag
User and privilege mode (read):
0 No interrupt occurred
1 Interrupt occurred
Privilege mode (write):
0 No influence on bit
1 Bit will be cleared
16 EO_BUFF End of Buffer Interrupt Flag
User and privilege mode (read):
0 No interrupt occurred
1 Interrupt occurred
Privilege mode (write):
0 No influence on bit
1 Bit will be cleared
15 DEST3REG2 Destination 3 Region 2 Interrupt Flag
User and privilege mode (read):
0 No interrupt occurred
1 Interrupt occurred
Privilege mode (write):
0 No influence on bit
1 Bit will be cleared
14 DEST3REG1 Destination 3 Region 1 Interrupt Flag
User and privilege mode (read):
0 No interrupt occurred
1 Interrupt occurred
Privilege mode (write):
0 No influence on bit
1 Bit will be cleared
1846
Data Modification Module (DMM) SPNU562–May 2014
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated