Datasheet

MDCLK
MDIO
(output)
1
7
3
MDCLK
MDIO
(input)
1
3
4
5
206
RM57L843
SPNS215C –FEBRUARY 2014–REVISED JUNE 2016 www.ti.com
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Peripheral Information and Electrical Specifications Copyright © 2014–2016, Texas Instruments Incorporated
(1) This is a discrepancy to IEEE 802.3, but is compatible with many PHY devices.
7.12.3 Management Data Input/Output (MDIO)
Figure 7-29. MDIO Input Timing
Table 7-42. MDIO Input Timing Requirements
NO. Parameter Value Unit
MIN MAX
1 tc(MDCLK) Cycle time, MDCLK 400 - ns
2 tw(MDCLK) Pulse duration, MDCLK high/low 180 - ns
3 tt(MDCLK) Transition time, MDCLK - 5 ns
4 tsu(MDIO-MDCLKH) Setup time, MDIO data input valid before MDCLK
High
12
(1)
- ns
5 th(MDCLKH-MDIO) Hold time, MDIO data input valid after MDCLK
High
1 - ns
Figure 7-30. MDIO Output Timing
Table 7-43. MDIO Output Timing Requirements
NO. Parameter Value Unit
MIN MAX
1 tc(MDCLK) Cycle time, MDCLK 400 - ns
7 td(MDCLKL-MDIO) Delay time, MDCLK low to MDIO data output
valid
0 100 ns