Datasheet

Level0 Interrupt to VIM
Level1 Interrupt to VIM
Module Interrupt
Flag
Interrupt Enable
Interrupt Level
www.ti.com Module Operation
35.2.3.1 Overflow Error
This error is signaled when the module has received new data before the previous data was written to the
destination address. If the internal buffers are full, the DMMENA signal will go high. If the sending module
does not evaluate the DMMENA signal and keeps on sending new frames, the data that was previously
received might be overwritten, thus resulting in setting the BUFF_OVF flag (Section 35.3.5).
35.2.3.2 Packet Error
Noncontinuous Clock Mode
The size of the incoming packet is defined by the SIZE information of a trace mode packet or the
programmed size of a direct data mode packet. If too many or less than the number of bits are received
before the next sync signal, the PACKET_ERR_INT flag will be set (Section 35.3.5). In case of receiving a
DMMCLK signal without a corresponding DMMSYNC signal, a packet error will also be generated.
Continuous Clock Mode
If less than the expected number of bits are received, the PACKET_ERR_INT flag will be set
(Section 35.3.5) when the next DMMSYNC signal is received. Packets with more than the expected
number of bits cannot be detected.
The check for packet error is done only after the detection of the first DMMSYNC signal after the DMM is
turned on or comes out of suspend mode (with COS = 0; Section 35.3.1 ), that is, before the reception of
first DMMSYNC, the toggling of DMMCLK would be ignored.
35.2.3.3 Bus Error
If an error occurs on the microcontroller internal bus system while transferring the data from the DMM to
the destination, the BUSERROR flag will be set.
35.2.4 Interrupts
The module provides different interrupts. These can be programmed to different interrupt levels
independently using DMMINTLVL (Section 35.3.4).
Figure 35-6. Interrupt Structure
Interrupts can be divided into error interrupts and functional interrupts. The error handling is described in
Section 35.2.3. Functional interrupts depend on the mode (Trace Mode, Direct Data Mode) the DMM
module is used in.
Trace Mode: An interrupt can be enabled whenever an access to the lowest address of a defined region
is performed. This address is the starting address programmed in the DMMDESTxREGy register. An
interrupt for each of the region can be generated by setting the individual interrupt enable bits.
Direct Data Mode: There are two interrupts which can be individually controlled. One is generated when
the buffer pointer reaches the end of the defined buffer and wraps around (EO_BUFF; Section 35.3.2).
The other one is generated when the buffer pointer matches the programmed interrupt threshold
(PROG_BUFF; Section 35.3.2). The buffer pointer points to the next address to be written, therefor there
are (interrupt threshold - 1) values stored in the buffer. The interrupt threshold can be programmed in the
DMMINTPT register (Section 35.3.11).
1831
SPNU562–May 2014 Data Modification Module (DMM)
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