Datasheet

1
2
3
RMII_REFCLK
RMII_TXEN
RMII_TXD[1:0]
RMII_RXD[1:0]
RMII_CRS_DV
RMII_RX_ER
6
7
11
9
8
5
4
10
5
205
RM57L843
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Peripheral Information and Electrical SpecificationsCopyright © 2014–2016, Texas Instruments Incorporated
7.12.2 Ethernet RMII Timing
Figure 7-28. RMII Timing Diagram
Table 7-41. RMII Timing Requirements
NO. Parameter Value Unit
MIN NOM MAX
1 tc(REFCLK) Cycle time, RMII_REF_CLK - 20 - ns
2 tw(REFCLKH) Pulse width, RMII_REF_CLK High 7 - 13 ns
3 tw(REFCLKL) Pulse width, RMII_REF_CLK Low 7 - 13 ns
6 tsu(RXD-REFCLK) Input setup time, RMII_RXD valid before
RMII_REF_CLK High
4 - - ns
7 th(REFCLK-RXD) Input hold time, RMII_RXD valid after
RMII_REF_CLK High
2 - - ns
8 tsu(CRSDV-REFCLK) Input setup time, RMII_CRSDV valid before
RMII_REF_CLK High
4 - - ns
9 th(REFCLK-CRSDV) Input hold time, RMII_CRSDV valid after
RMII_REF_CLK High
2 - - ns
10 tsu(RXER-REFCLK) Input setup time, RMII_RXER valid before
RMII_REF_CLK High
4 - - ns
11 th(REFCLK-RXER) Input hold time, RMII_RXER valid after
RMII_REF_CLK High
2 - - ns
4 td(REFCLK-TXD) Output delay time, RMII_REF_CLK High to
RMII_TXD valid
2 - 16 ns
5 td(REFCLK-TXEN) Output delay time, RMII_REF_CLK High to
RMII_TX_EN valid
2 - 16 ns