Datasheet
ePWM Registers
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34.4.8.9 Digital Compare Counter Capture Register (DCCAP)
Figure 34-99. Digital Compare Counter Capture Register (DCCAP) [offset = 72h]
15 0
DCCAP
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 34-59. Digital Compare Counter Capture Register (DCCAP) Field Descriptions
Bit Field Description
15-0 DCCAP Digital Compare Time-Base Counter Capture
To enable time-base counter capture, set the DCCAPCLT[CAPE] bit to 1.
If enabled, reflects the value of the time-base counter (TBCTR) on the low to high edge transition of a
filtered (DCEVTFLT) event. Further capture events are ignored until the next period or zero as selected by
the DCFCTL[PULSESEL] bit.
Shadowing of DCCAP is enabled and disabled by the DCCAPCTL[SHDWMODE] bit. By default this
register is shadowed.
• If DCCAPCTL[SHDWMODE] = 0, then the shadow is enabled. In this mode, the active register is copied
to the shadow register on the TBCTR = TBPRD or TBCTR = zero as defined by the
DCFCTL[PULSESEL] bit. CPU reads of this register will return the shadow register value.
• If DCCAPCTL[SHDWMODE] = 1, then the shadow register is disabled. In this mode, CPU reads will
return the active register value.
The active and shadow registers share the same memory map address.
34.4.8.10 Digital Compare Filter Window Counter Register (DCFWINDOWCNT)
Figure 34-100. Digital Compare Filter Window Counter Register (DCFWINDOWCNT) [offset = 70h]
15 8
Reserved
R-0
7 0
WINDOWCNT
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 34-60. Digital Compare Filter Window Counter Register (DCFWINDOWCNT) Field
Descriptions
Bit Field Value Description
15-8 Reserved 0 Any writes to these bit(s) must always have a value of 0.
7-0 WINDOWCNT 0-FFh Blanking Window Counter
These 8 bits are read only and indicate the current value of the window counter. The counter
counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again.
1824
Enhanced Pulse Width Modulator (ePWM) Module SPNU562–May 2014
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