Datasheet

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34.4.8.7 Digital Compare Filter Window Register (DCFWINDOW)
Figure 34-97. Digital Compare Filter Window Register (DCFWINDOW) [offset = 6Eh]
15 8
Reserved
R-0
7 0
WINDOW
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 34-57. Digital Compare Filter Window Register (DCFWINDOW) Field Descriptions
Bit Field Value Description
15-8 Reserved 0 Reserved
7-0 WINDOW Blanking Window Width
0 No blanking window is generated.
1h-FFh Specifies the width of the blanking window in TBCLK cycles. The blanking window begins
when the offset counter expires. When this occurs, the window counter is loaded and begins
to count down. If the blanking window is currently active and the offset counter expires, the
blanking window counter is restarted.
The blanking window can cross a PWM period boundary.
34.4.8.8 Digital Compare Filter Offset Counter Register (DCFOFFSETCNT)
Figure 34-98. Digital Compare Filter Offset Counter Register (DCFOFFSETCNT) [offset = 6Ch]
15 0
OFFSETCNT
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 34-58. Digital Compare Filter Offset Counter Register (DCFOFFSETCNT) Field Descriptions
Bit Field Description
15-0 OFFSETCNT Blanking Offset Counter
These 16-bits are read only and indicate the current value of the offset counter. The counter counts down
to zero and then stops until it is re-loaded on the next period or zero event as defined by the
DCFCTL[PULSESEL] bit.
The offset counter is not affected by the free/soft emulation bits. That is, it will always continue to count
down if the device is halted by a emulation stop.
1823
SPNU562–May 2014 Enhanced Pulse Width Modulator (ePWM) Module
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